{"id":79394,"date":"2024-10-17T18:34:00","date_gmt":"2024-10-17T18:34:00","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/ieee-896-2-1992\/"},"modified":"2024-10-24T19:39:59","modified_gmt":"2024-10-24T19:39:59","slug":"ieee-896-2-1992","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/ieee\/ieee-896-2-1992\/","title":{"rendered":"IEEE 896.2 1992"},"content":{"rendered":"

New IEEE Standard – Inactive – Withdrawn. Futurebus+ standards provide systems developers a set of tools with which high-performance bus-based systems may be developed. This architecture provides a wide range of performance scalability over both cost and time for multiple generations of single- and multiple-bus multiprocessor systems. This document, a companion standard to IEEE Std. 896.1-1991, builds on the logical layer by adding requirements for physical layer instantiation. Material in this document includes specifications for node management, live insertion, and profiles. It is to these profiles that products will claim conformance. Other specifications that may be required in conjunction with this standard are the following: IEEE Std 896.1-1991; P896.3, Futurebus+ Recommended Practices; P1212.x, Control and Status Register Architectures; IEEE Std 1194.1-1991, Electrical Characteristics of Backplane Transceiver Logic (BTL) Interface Circuits; and IEEE Std 1301.x, Metric Equipment Practices for Microcomputers.<\/p>\n

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PDF Pages<\/th>\nPDF Title<\/th>\n<\/tr>\n
5<\/td>\nU BOU N D-H <\/td>\n<\/tr>\n
7<\/td>\nI BIT FIELD I REQ I ACCESS IPOWER-UP1 SYSTEM I BUS <\/td>\n<\/tr>\n
16<\/td>\nTable <\/td>\n<\/tr>\n
17<\/td>\nIn tr o ducti on
1.1 Scope
Fig <\/td>\n<\/tr>\n
18<\/td>\n1.2 References
1.2.1 Protocol Stack Specifications
Control
Fig <\/td>\n<\/tr>\n
19<\/td>\nDefinitions and Structure
2.1 Special Word Usage <\/td>\n<\/tr>\n
20<\/td>\n2.2 Definitions <\/td>\n<\/tr>\n
24<\/td>\n2.3 Signal Conventions
2.4 Numbering Conventions
Signal Conventions <\/td>\n<\/tr>\n
25<\/td>\n2.5 Futurebus+ Logo
Numbering Conventions
IEEE 896 Logo <\/td>\n<\/tr>\n
26<\/td>\nAddress Space
3.1.1.1 Memory Addresses <\/td>\n<\/tr>\n
27<\/td>\nFuturebus+ Boards Modules and Nodes
32-bit CSR Addressing <\/td>\n<\/tr>\n
28<\/td>\n3.1.1.3 Hybrid Addressing
32-bit CSR Addressing
First CSR Address of Local Bus Node One <\/td>\n<\/tr>\n
29<\/td>\nByte Lane Mapping
Hybrid Addressing <\/td>\n<\/tr>\n
30<\/td>\nBase Functional Character
Native Big Endian Node to Futurebus+ CSR Byte Lane Mapping
Native Little Endian Node to Futurebus+ CSR Byte Lane Mapping <\/td>\n<\/tr>\n
31<\/td>\n3.1.2.1 Resets
3.1.2.2 ROM Identification
Reset (RE*) Operations
Basic Node ROM Structure <\/td>\n<\/tr>\n
32<\/td>\n3.1.2.3 Capability and Setup
3.1.2.4 Bus Control <\/td>\n<\/tr>\n
33<\/td>\n3.1.2.5 Distributed Arbitration
Timeout and Setup <\/td>\n<\/tr>\n
34<\/td>\n3.1.2.7 Retry
Node State Control <\/td>\n<\/tr>\n
35<\/td>\n3.1.2.9 Standard Diagnostic Interface
Table <\/td>\n<\/tr>\n
36<\/td>\nTable <\/td>\n<\/tr>\n
37<\/td>\nOptional Functional Character
3.1.3.1 Messages <\/td>\n<\/tr>\n
38<\/td>\n3.1.3.2 Arbitrated Messages <\/td>\n<\/tr>\n
39<\/td>\n3.1.3.3 Interrupts
Comparison of Interrupt Registers <\/td>\n<\/tr>\n
40<\/td>\n3.1.3.4 Packet Management
3.1.3.5 Clock Synchronization <\/td>\n<\/tr>\n
44<\/td>\n3.1.3.6 Unit Access <\/td>\n<\/tr>\n
45<\/td>\nClock Synchronization <\/td>\n<\/tr>\n
46<\/td>\nFuturebus+ CSR Specification
3.2.1 CSR Memory Space Specification <\/td>\n<\/tr>\n
47<\/td>\n3.2.2 Core CSRs
CSR Address Space Allocation <\/td>\n<\/tr>\n
48<\/td>\nSTATE-CLEAR and STATE-SET CSRs
Core CSRs and Addresses <\/td>\n<\/tr>\n
49<\/td>\nSTATE-CLEAR and STATE-SET CSR Bit Descriptions <\/td>\n<\/tr>\n
50<\/td>\n3.2.2.2 NODE-IDS CSR
Fields in the STATE-CLEAR and STATE-SET CSRs Used by Futurebus+
NODE-IDS CSR Bit Descriptions <\/td>\n<\/tr>\n
51<\/td>\n3.2.2.3 RESET-START CSR
Format of the NODE-IDS CSR <\/td>\n<\/tr>\n
52<\/td>\nInternal Indirect Address Space CSRs
Format of the RESET-START CSR
Format of the Internal INDIRECT-ADDRESS CSR
Internal INDIRECT-ADDRESS CSR Bit Description <\/td>\n<\/tr>\n
53<\/td>\n3.2.2.5 SPLIT-TIMEOUT CSR
Format of the Internal INDIRECT-DATA CSR
Internal INDIRECT-DATA CSR Bit Description
SPLIT-TIMEOUT CSR Bit Description <\/td>\n<\/tr>\n
54<\/td>\nFormat of the SPLIT-TIMEOUT CSRs
ARGUMENT CSRs Bit Description <\/td>\n<\/tr>\n
55<\/td>\n3.2.2.7 TEST-START CSR
Fig 14 (a) General Format of the ARGUMENT CSRs
Extended Test Category Format of the Argument CSRs <\/td>\n<\/tr>\n
56<\/td>\nTEST-START CSR Bit Descriptions <\/td>\n<\/tr>\n
57<\/td>\nFormat of the TEST-START CSR <\/td>\n<\/tr>\n
58<\/td>\nTEST-STATUS CSR Bit Descriptions <\/td>\n<\/tr>\n
60<\/td>\nExtended Units Address Space CSRs
Format of the TEST-STATUS CSR <\/td>\n<\/tr>\n
61<\/td>\nFormat of the UNITS-BASE CSR
Format of the UNITS-BOUND CSR
UNITS-BASE CSR Bit Description
UNITS-BOUND CSR Bit Description <\/td>\n<\/tr>\n
62<\/td>\nMemory Unit Address Space CSRs
Format of the MEMORY-BASE CSR
MEMORY-BASE CSR Bit Description <\/td>\n<\/tr>\n
63<\/td>\nINTERRUPT-TARGET and INTERRUPT-MASK CSRs
Format of the MEMORY-BOUND CSR
MEMORY-BOUND CSR Bit Description
INTERRUPT-TARGET CSR Bit Description <\/td>\n<\/tr>\n
64<\/td>\nCSRs for Clock Synchronization
INTERRUPT-MASK CSR Bit Description
CLOCK-VALUE CSR Bit Description <\/td>\n<\/tr>\n
65<\/td>\nCLOCK-TICK-PERIOD CSR Bit Description
CLOCK-STROBE-ARRIVED CSR Bit Description <\/td>\n<\/tr>\n
67<\/td>\nMessage Target CSRs
3.2.2.14 Error Symptom CSRs
CLOCK-REFERENCE CSR Bit Description
MESSAGE-REQUEST CSR Bit Description
MESSAGE-RESPONSE CSR Bit Description <\/td>\n<\/tr>\n
68<\/td>\nERROR-HI CSR Bit Descriptions <\/td>\n<\/tr>\n
70<\/td>\nERROR-HI CSR Format (Most Significant Half)
ERROR-HI CSR Format (Least Significant Half) <\/td>\n<\/tr>\n
71<\/td>\nERROR-LO CSR Bit Descriptions <\/td>\n<\/tr>\n
72<\/td>\nFormat of the ERROR-LO CSR <\/td>\n<\/tr>\n
73<\/td>\nFAILING-ADDRESS CSR
BYTE-LANE-IN-ERROR CSR
DATA-HOLD CSR
TAG-HOLD CSR <\/td>\n<\/tr>\n
74<\/td>\nFuturebus+ Dependent CSR Area
Fig 24 Format of the TAG-HOLD Register
TIME-STAMP CSR <\/td>\n<\/tr>\n
75<\/td>\n3.2.3.1 LOGICAL-COMMON-CONTROL CSR
Futurebus+ Specific CSRs
LOGICAL-COMMON-CONTROL CSR Bit Descriptions <\/td>\n<\/tr>\n
76<\/td>\nFormat of the LOGICAL-COMMON-CONTROL CSR <\/td>\n<\/tr>\n
77<\/td>\n3.2.3.2 LOGICAL-MODULE-CONTROL CSR
LOGICAL-MODULE-CONTROL CSR Bit Descriptions <\/td>\n<\/tr>\n
79<\/td>\n3.2.3.3 BUS-PROPAGATION-DELAY CSR
Format ofthe LOGICAL-MODULE-CONTROL CSR <\/td>\n<\/tr>\n
80<\/td>\n3.2.3.4 COMPETITION-SETTLING-TIME CSR
BUS-PROPAGATION-DELAY CSR Bit Descriptions
Table 39 COMPETITION-SETTLING-TIME CSR Bit Descriptions <\/td>\n<\/tr>\n
81<\/td>\n3.2.3.6 MESSAGE-PASSING-SELECT-MASK CSR
Busy Retry CSRs
MESSAGE-PASSING-SELECT-MASK CSR Bit Descriptions
Table <\/td>\n<\/tr>\n
82<\/td>\nFig 27 BUSY-RETRY-COUNTER CSR
BUSY-RETRY-COUNTER CSR Bit Descriptions
Table <\/td>\n<\/tr>\n
83<\/td>\nError Retry CSRs
BUSY-RETRY-DELAY CSR <\/td>\n<\/tr>\n
84<\/td>\nERROR-RETRY-COUNTER CSR
ERROR-RETRY-COUNTER CSR Bit Descriptions
Table
ERROR-RETRY-DELAY CSR Bit Descriptions
Table <\/td>\n<\/tr>\n
85<\/td>\nBus Specific ROM Entries
ERROR-RETRY-DELAY CSR <\/td>\n<\/tr>\n
86<\/td>\nTable 46 Node ROM Specified Locations <\/td>\n<\/tr>\n
87<\/td>\n3.2.4.1 Bus Information Block
3.2.4.2 MODULE-LOGICAL-CAPABILITY
Futurebus+ Required BUS INFORMATION BLOCK ROM Entries
Table <\/td>\n<\/tr>\n
88<\/td>\nMODULE-LOGICAL-CAPABILITY CSR Bit Descriptions
Table <\/td>\n<\/tr>\n
90<\/td>\nFig 31 (a) MODULE-LOGICAL-CAPABILITY (Most Significant Half)
MODULE-LOGICAL-CAPABILITY (Least Significant Half) <\/td>\n<\/tr>\n
91<\/td>\n3.2.4.3 NODE-CAPABILITIES-EXT
NODE-CAPABILITIES-EXT CSR Bit Descriptions
Table <\/td>\n<\/tr>\n
92<\/td>\n3.2.4.4 COMPETITION-INTERNAL-DELAY CSR
Format of the NODE-CAPABILITIES-EXT CSR <\/td>\n<\/tr>\n
93<\/td>\n3.2.4.5 PACKET-SPEED CSR
3.2.4.6 MESSAGE-FRAME-SIZE CSR
Format of the COMPETITION-INTERNAL-DELAY CSR
Format of the PACKET-SPEED CSR <\/td>\n<\/tr>\n
94<\/td>\nBusy Retry Capability CSRs
Error Retry Capability CSRs
Format of the MESSAGE-FRAME-SIZE CSR <\/td>\n<\/tr>\n
95<\/td>\nCore CSR Root Directory
Table 50 (a) ROM Directory Entry Format
Table 50 (b) Directory \u00ef\u00ac\u0081Key Type\u00ef\u00ac\u201a Definitions
Table 50 (c) Directory Entry Keys <\/td>\n<\/tr>\n
97<\/td>\n3.2.5.1 MODULE-VENDOR-ID ROM Entry
MODULE-SPEC-ID ROM Entry
NODE-CAPABILITIES ROM Entry <\/td>\n<\/tr>\n
98<\/td>\nNODE-CAPABILITIES CSR Bit Descriptions <\/td>\n<\/tr>\n
99<\/td>\nMODULE-HW-VERSION ROM Entry
Bus Visible Address RAM
Format of the NODE-CAPABILITIES Entry <\/td>\n<\/tr>\n
100<\/td>\nFormat of the NODE-MEMORY-EXTENT Entry
MEMORY-EXTENT Bit Descriptions <\/td>\n<\/tr>\n
101<\/td>\nVendor-Defined ROM Entries
MODULE-VENDOR-DEPENDENT-INFO ROM Entry
Initial Units Space
Interrupts
Format of the NODE-UNITS-EXTENT Entry
UNITS-EXTENT Bit Descriptions <\/td>\n<\/tr>\n
102<\/td>\nDistributed Arbitration Messages and General Arbitrated Messages <\/td>\n<\/tr>\n
103<\/td>\nLive Insertion
4.1 Description
4.1.1 Introduction
4.1.2 General Considerations
4.1.3 Levels of Live Insertion <\/td>\n<\/tr>\n
104<\/td>\nLevel 1 Live Insertion and Withdrawal
Level 2 Live Insertion and Withdrawal
Level 3 Live Insertion and Withdrawal <\/td>\n<\/tr>\n
105<\/td>\n4.1.4 Operator Facilities
Live Insertion State Diagram <\/td>\n<\/tr>\n
106<\/td>\nLive Insertion Module State Diagram
Node Indicator Relationship to State <\/td>\n<\/tr>\n
107<\/td>\nConceptual Module Design <\/td>\n<\/tr>\n
109<\/td>\n4.2 Specification
4.2.1 Definitions
System Operation Requirements
Functional Design of a Live Insertion Module <\/td>\n<\/tr>\n
110<\/td>\nLive Insertion Power Requirements
4.2.4 Module Activation and Deactivation
Live Insertion ESD Requirements
4.2.6 Live Insertion Electrical Requirements
Level 1 Requirements
Level 2 Requirements <\/td>\n<\/tr>\n
111<\/td>\nLevel 3 Requirements
Futurebus+ Live Insertion Glyph
Definition of SWAP Indicator
Futurebus+ Live Insertion Glyph <\/td>\n<\/tr>\n
112<\/td>\n5 Introduction to Application Environment Profiles
Application Environment Profile (AEP) Description
Futurebus+ Open Systems Protocol Stack <\/td>\n<\/tr>\n
113<\/td>\nMinimum Requirements for AEPs (AEP Specification)
AEP Terminology and Definitions
Organization <\/td>\n<\/tr>\n
114<\/td>\nProfile Content
5.2.3.1 Arbitration
5.2.3.2 Parallel Protocol <\/td>\n<\/tr>\n
115<\/td>\nTiming Specification
Global Timing Specifications
Timing Specifications for (Arbitration Type) Arbitration
Timing Specifications for the Arbitrated Message Bus Used for Messages
Timing Specifications for the Parallel Protocol <\/td>\n<\/tr>\n
116<\/td>\nCSRs
Cache Coherence
Message Passing
Systems Configurations
Physical Layer
5.2.4.1 Power Supply Specifications <\/td>\n<\/tr>\n
117<\/td>\nProfile Electrical and Signaling Environment <\/td>\n<\/tr>\n
118<\/td>\n5.2.4.3 Live Insertion
5.2.4.4 Mechanical <\/td>\n<\/tr>\n
119<\/td>\n5.2.4.5 InpuVOutput
5.2.4.6 Connector and Pinout Assignment
Environmental
Standards Requirements <\/td>\n<\/tr>\n
120<\/td>\nApplication Environment Profile A
6.1 Reference Specification
6.1.1 Introduction
Target Market and Applications
6.1.3 Terminology
6.1.4 Referenced Documents
6.1.5 Reference Tables
6.1.6 Profiles Interoperability <\/td>\n<\/tr>\n
121<\/td>\nProfile A Logical Layer Referenced Specifications <\/td>\n<\/tr>\n
123<\/td>\nProfile A Physical Layer Referenced Specifications <\/td>\n<\/tr>\n
125<\/td>\n6.2 Detailed Specification
Arbitration <\/td>\n<\/tr>\n
126<\/td>\nParallel Protocol
6.2.2.1 Transaction Types <\/td>\n<\/tr>\n
127<\/td>\n6.2.2.2 Tag Bits
6.2.2.3 Serial Bus
Busmode Management and CSRs
6.2.3.1 Addressing
Byte-Lane Wiring and Byte Ordering
6.2.3.3 Interrupts
6.2.3.4 Diagnostics and Test <\/td>\n<\/tr>\n
128<\/td>\n6.2.3.5 CSRs
CSR Address Space
Profile A Core CSRs <\/td>\n<\/tr>\n
130<\/td>\nProfile A Specific CSRs <\/td>\n<\/tr>\n
131<\/td>\nCache Coherence
Message Passing
System Configuration
Profile A ROM Registers <\/td>\n<\/tr>\n
132<\/td>\n6.2.6.1 Monarch Selection
Profile A Power
6.2.7.1 Module Power <\/td>\n<\/tr>\n
134<\/td>\n6.2.8 Profile A Electrical
6.2.8.1 Signal Integrity
Profile A Power Rails <\/td>\n<\/tr>\n
135<\/td>\nFunctional Electrical Requirements
Live Insertion and Withdrawal <\/td>\n<\/tr>\n
136<\/td>\n6.2.9.1 Alignment
Live Insertion Power
Live Insertion and Withdrawal Safety <\/td>\n<\/tr>\n
137<\/td>\n6.2.10 Mechanical
Specifications <\/td>\n<\/tr>\n
138<\/td>\nView of Subrack\/Backplane Relationship <\/td>\n<\/tr>\n
139<\/td>\nConnector <\/td>\n<\/tr>\n
140<\/td>\nView of Plug-in Module <\/td>\n<\/tr>\n
141<\/td>\nDetail \u00ef\u00ac\u0081C \u00ef\u00ac\u201a Alignment Pin Position on Front Panel and Subrack <\/td>\n<\/tr>\n
142<\/td>\nDetail \u00ef\u00ac\u0081B \u00ef\u00ac\u201a Front Panel Section <\/td>\n<\/tr>\n
143<\/td>\nand Alignment Pin Position <\/td>\n<\/tr>\n
144<\/td>\nDesign Features <\/td>\n<\/tr>\n
146<\/td>\nHeights X-Z View <\/td>\n<\/tr>\n
147<\/td>\nCalculation of Maximum Component Heights <\/td>\n<\/tr>\n
148<\/td>\nProfile A Front Panel Organization <\/td>\n<\/tr>\n
150<\/td>\nEM1 Considerations
Module Status State Diagram <\/td>\n<\/tr>\n
151<\/td>\nEMI\/RFI Shielding Locations and Interfacing Surfaces-Preferred <\/td>\n<\/tr>\n
152<\/td>\n6.2.10.4 Injector\/Ejector Mechanism
EMI\/RFI Shielding Locations and Interfacing Surfaces Alternative <\/td>\n<\/tr>\n
153<\/td>\nBus Connector Mechanical
6.2.11 Inputloutput
Profile A Connector Power and Signal Pin Assignment
Assignment <\/td>\n<\/tr>\n
154<\/td>\nSignal Pin Assignment
Connector Naming Conventions <\/td>\n<\/tr>\n
155<\/td>\nPower Pin Assignment
6.2.12.4 Connector Keying
Environmental Specifications and Other Standards Compliance <\/td>\n<\/tr>\n
156<\/td>\nConnector B and X Pinouts for 64\/32-Bit Address and Data Paths <\/td>\n<\/tr>\n
157<\/td>\nConnector E Pinout for 128-Bit Data Path Extension <\/td>\n<\/tr>\n
158<\/td>\nConnector E Pinout for 192 I\/O <\/td>\n<\/tr>\n
159<\/td>\nConnector E Pinout for 128-Bit Extension and 80 I\/O <\/td>\n<\/tr>\n
160<\/td>\nSubrack Air Flow and Thermal Considerations
Profile A Power Connector Pin Assignment <\/td>\n<\/tr>\n
161<\/td>\n6.2.13.2 Safety and EM1 Standards <\/td>\n<\/tr>\n
162<\/td>\nApplication Environment Profile B
7.1 Reference Specification
7.1.1 Introduction
Target Market and Applications
7.1.3 Profile B Terminology
7.1.4 Referenced Documents
7.1.5 Reference Tables
Profile B Logical Layer Referenced Specifications <\/td>\n<\/tr>\n
164<\/td>\nProfile B Physical Layer Referenced Specifications <\/td>\n<\/tr>\n
166<\/td>\nMultiple Profile Interoperability
7.2 Detailed Specification
Arbitration
7.2.1.1 Central Arbitration <\/td>\n<\/tr>\n
167<\/td>\n7.2.1.2 Distributed Arbitration
Parallel Protocol
7.2.2.1 Transaction Types <\/td>\n<\/tr>\n
168<\/td>\n7.2.2.2 Prohibited Operations <\/td>\n<\/tr>\n
169<\/td>\n7.2.2.3 Timing Specifications
Global Timing Specifications
Timing Specifications for Central Arbitration <\/td>\n<\/tr>\n
170<\/td>\n7.2.2.4 Tag Bits
the Power Fail
Timing Specifications for the Parallel Protocol <\/td>\n<\/tr>\n
171<\/td>\n7.2.2.5 Serial Bus
Busmode Management and CSRs
7.2.3.1 Addressing
Byte Ordering
7.2.3.3 Interrupts
7.2.3.4 DMA
and Test
CSRs
CSR Address Space <\/td>\n<\/tr>\n
172<\/td>\nProfile B Core CSRs <\/td>\n<\/tr>\n
173<\/td>\nProfile B Futurebus+ Specific CSRs <\/td>\n<\/tr>\n
174<\/td>\nCaching and Cache Coherence
Message Passing
Profile B ROM Registers <\/td>\n<\/tr>\n
175<\/td>\nSystem Configuration
Profile B Power
7.2.7.1 Module Power
7.2.7.2 System Power Supplies <\/td>\n<\/tr>\n
177<\/td>\nProfile B Power Rails
Profile B Power Supply Sequencing <\/td>\n<\/tr>\n
179<\/td>\nProfile B Electrical
7.2.8.1 Signal Integrity <\/td>\n<\/tr>\n
180<\/td>\nBackplane Characteristics <\/td>\n<\/tr>\n
181<\/td>\nFunctional Electrical Requirements
Module Signal Line Characteristics <\/td>\n<\/tr>\n
183<\/td>\nLive Insertion and Withdrawal
Level 1 Live Insertion <\/td>\n<\/tr>\n
184<\/td>\nLevel 2 Live Insertion
7.2.9.3 Alignment
Live Insertion Power
Live Insertion and Withdrawal Safety
Mechanical <\/td>\n<\/tr>\n
185<\/td>\n7.2.10.1 Subrack Mechanical Specifications <\/td>\n<\/tr>\n
186<\/td>\nX-Y View of Subrack and Module Relationship <\/td>\n<\/tr>\n
187<\/td>\nDesign Features
Installed Connector <\/td>\n<\/tr>\n
188<\/td>\nCalculation of Maximum Component Heights <\/td>\n<\/tr>\n
189<\/td>\nY-Z View of Plug-in Unit <\/td>\n<\/tr>\n
190<\/td>\nX-Y View of Plug-in Unit <\/td>\n<\/tr>\n
191<\/td>\nRecommended Injector\/Ejector Lever for Profile B <\/td>\n<\/tr>\n
192<\/td>\nHeights X-Z View <\/td>\n<\/tr>\n
194<\/td>\nProfile B Front Panel Organization
Fig <\/td>\n<\/tr>\n
195<\/td>\nModule Status State Diagram
Fig <\/td>\n<\/tr>\n
196<\/td>\n7.2.10.3 EM1 Considerations <\/td>\n<\/tr>\n
197<\/td>\nEMI\/RFI Shielding Locations and Interfacing Surfaces-Preferred
Fig <\/td>\n<\/tr>\n
198<\/td>\n7.2.10.4 Injector\/Ejector Mechanism
EMI\/RFI Shielding Locations and Interfacing Surfaces-Alternative
Fig <\/td>\n<\/tr>\n
199<\/td>\nBus Connector Mechanical
Inputloutput
Profile B Connector Power and Signal Pin Assignment
Assignment <\/td>\n<\/tr>\n
200<\/td>\nSignal Pin Assignment
Connector Naming Conventions
Fig <\/td>\n<\/tr>\n
201<\/td>\nConnectors B and X Pinouts for 64\/32-Bit Address and Data Paths
Fig <\/td>\n<\/tr>\n
202<\/td>\nConnector E Pinout for 128-Bit Extension and 80 1\/0
Fig <\/td>\n<\/tr>\n
203<\/td>\nPower Pin Assignment
Profile B Power Connector Pin Assignment
Fig <\/td>\n<\/tr>\n
204<\/td>\nEnvironmental Specifications and Other Standards Compliance
Subrack Air Flow and Thermal Considerations
7.2.13.2 Safety and EM1 Standards <\/td>\n<\/tr>\n
205<\/td>\nApplication Environment Profile F
8.1 Reference Specifications
8.1.1 Introduction
Target Market and Applications
8.1.3 Profile F Terminology
8.1.4 IEEE Standards Referenced
8.1.5 Reference Tables <\/td>\n<\/tr>\n
206<\/td>\nProfile F Logical Layer Referenced Specifications <\/td>\n<\/tr>\n
207<\/td>\nMultiple Profile Interoperability
8.1.6.1 Profile A Interoperability
Profile B Interoperability <\/td>\n<\/tr>\n
208<\/td>\n8.2 Detailed Specification
8.2.1 Arbitration
8.2.2 Parallel Protocol <\/td>\n<\/tr>\n
209<\/td>\n8.2.2.1 Transaction Types
8.2.2.2 Split Transactions
8.2.2.3 Locked Operations
8.2.2.4 Packet Data Transfers <\/td>\n<\/tr>\n
210<\/td>\n8.2.2.5 Busy
8.2.2.6 Tag Bits
8.2.2.7 Serial Bus
Retry Delay Times <\/td>\n<\/tr>\n
211<\/td>\n8.2.3 Timing Specifications
Global Timing Specifications <\/td>\n<\/tr>\n
212<\/td>\nTiming Specifications for Central Arbitration
Timing Specifications for Arbited Messages
Timing Specifications for the Parallel Protocol <\/td>\n<\/tr>\n
214<\/td>\nBudsystem Management and CSRs
8.2.4.1 Addressing
8.2.4.2 Byte-Lane Wiring and Byte Ordering
8.2.4.3 Interrupts
8.2.4.4 Diagnostics and Test
8.2.4.5 CSRs
Profile F Core CSRs <\/td>\n<\/tr>\n
216<\/td>\nProfile F Futurebus+ Specific CSRs
Profile F ROM CSRs <\/td>\n<\/tr>\n
217<\/td>\nCaching and Cache Coherence
Message Passing
System Configuration
Monarch Selection Description <\/td>\n<\/tr>\n
218<\/td>\nMonarch Selection Attribute Specification
Power Supply
Electrical
Wire-OR Glitch Filters
Live Insertion and Withdrawal
Mechanical
InputlOutput
Connector Power and Signal Pin Assignment
Non-Central Arbiter Slot
8.2.13.2 Central Arbiter Slot <\/td>\n<\/tr>\n
219<\/td>\nConnector E Pinout for Central Arbiter Slot
Fig <\/td>\n<\/tr>\n
220<\/td>\nEnvironmental
Specification for a Module-Based Central Arbiter
8.3.1 Backplane Requirements
8.3.1.1 Wiring
Geographical Address Assignment
Backplane Delay Encoding on BD[2 01* <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":"

IEEE Standard Backplane Bus Specification for Multiprocessor Architectures: Futurebus+(R)<\/b><\/p>\n\n\n\n\n
Published By<\/td>\nPublication Date<\/td>\nNumber of Pages<\/td>\n<\/tr>\n
IEEE<\/b><\/a><\/td>\n1992<\/td>\n222<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n","protected":false},"featured_media":79395,"template":"","meta":{"rank_math_lock_modified_date":false,"ep_exclude_from_search":false},"product_cat":[2644],"product_tag":[],"class_list":{"0":"post-79394","1":"product","2":"type-product","3":"status-publish","4":"has-post-thumbnail","6":"product_cat-ieee","8":"first","9":"instock","10":"sold-individually","11":"shipping-taxable","12":"purchasable","13":"product-type-simple"},"_links":{"self":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product\/79394","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product"}],"about":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/types\/product"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media\/79395"}],"wp:attachment":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media?parent=79394"}],"wp:term":[{"taxonomy":"product_cat","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_cat?post=79394"},{"taxonomy":"product_tag","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_tag?post=79394"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}