This part of IEC 63093 specifies the dimensions that are of importance for mechanical interchangeability for a preferred range of EER-cores made of ferrite, the essential dimensions of coil formers to be used with them as well the effective parameter values to be used in calculations involving them, and gives guidelines on allowable limits of surface irregularities applicable to EER-cores.<\/p>\n
This document is a specification useful in the negotiations between ferrite core manufacturers and customers about surface irregularities.<\/p>\n
The use of \u201cderived\u201d standards which give more detailed specifications of component parts while still permitting compliance with this document is discussed in Annex A.<\/p>\n
| PDF Pages<\/th>\n | PDF Title<\/th>\n<\/tr>\n | ||||||
|---|---|---|---|---|---|---|---|
| 2<\/td>\n | undefined <\/td>\n<\/tr>\n | ||||||
| 6<\/td>\n | CONTENTS <\/td>\n<\/tr>\n | ||||||
| 8<\/td>\n | FOREWORD <\/td>\n<\/tr>\n | ||||||
| 10<\/td>\n | 1 Scope 2 Normative references 3 Terms and definitions 4 Primary dimensions 4.1 General <\/td>\n<\/tr>\n | ||||||
| 11<\/td>\n | 4.2 Dimensions of EER-cores 4.2.1 Principal dimensions Figures Figure 1 \u2013 Dimensions of EER-cores Tables Table 1 \u2013 Dimensions of EER-cores <\/td>\n<\/tr>\n | ||||||
| 12<\/td>\n | 4.2.2 Effective parameter and Amin values 4.3 Dimensional limits for coil formers Figure 2 \u2013 Essential dimensions of coil formers Table 2 \u2013 Effective parameter values of EER-cores <\/td>\n<\/tr>\n | ||||||
| 13<\/td>\n | 5 Limits of surface irregularities 5.1 General Figure 3 \u2013 Examples of surface irregularities Table 3 \u2013 Dimensional limits for coil formers <\/td>\n<\/tr>\n | ||||||
| 14<\/td>\n | 5.2 Chips and ragged edges 5.2.1 General 5.2.2 Chips and ragged edges on the mating surfaces (see Figure 4) 5.2.3 Chips and ragged edges on the other surfaces (see Figure 4) Figure 4 \u2013 Chip locations for EER-cores <\/td>\n<\/tr>\n | ||||||
| 15<\/td>\n | Table 4 \u2013 Area and length reference for visual inspection <\/td>\n<\/tr>\n | ||||||
| 16<\/td>\n | 5.3 Cracks 5.4 Flash 5.5 Pull-outs Figure 5 \u2013 Cracks and pull-out locations for EER-cores <\/td>\n<\/tr>\n | ||||||
| 17<\/td>\n | 5.6 Crystallites Figure 6 \u2013 Crystallite location for EER-cores Table 5 \u2013 Limits for cracks <\/td>\n<\/tr>\n | ||||||
| 18<\/td>\n | 5.7 Pores Figure 7 \u2013 Pore location for EER-cores <\/td>\n<\/tr>\n | ||||||
| 19<\/td>\n | Annex A (normative) Derived standards <\/td>\n<\/tr>\n | ||||||
| 20<\/td>\n | Annex B (normative) Example of dimensions for gauges to check the dimensions of EER-cores meeting this primary standard B.1 General B.2 Procedure and requirements Figure B.1 \u2013 Gauge dimensions Table B.1 \u2013 Gauge dimensions <\/td>\n<\/tr>\n | ||||||
| 21<\/td>\n | Annex C (informative) Examples of allowable areas of chips Table C.1 \u2013 Allowable areas of chips for EER-cores <\/td>\n<\/tr>\n | ||||||
| 22<\/td>\n | Bibliography <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":" Ferrite cores. Guidelines on dimensions and the limits of surface irregularities – EER-cores<\/b><\/p>\n |