{"id":397807,"date":"2024-10-20T04:32:23","date_gmt":"2024-10-20T04:32:23","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/ieee-802-3-2012-4\/"},"modified":"2024-10-26T08:20:28","modified_gmt":"2024-10-26T08:20:28","slug":"ieee-802-3-2012-4","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/ieee\/ieee-802-3-2012-4\/","title":{"rendered":"IEEE 802.3-2012"},"content":{"rendered":"

Revision Standard – Superseded. Ethernet local area network operation is specified for selected speeds of operation from 1 Mb\/s to 100 Gb\/s using a common media access control (MAC) specification and management information base (MIB). The Carrier Sense Multiple Access with Collision Detection (CSMA\/CD) MAC protocol specifies shared medium (half duplex) operation, as well as full duplex operation. Speed specific Media Independent Interfaces (MIIs) allow use of selected Physical Layer devices (PHY) for operation over coaxial, twisted-pair or fiber optic cables. System considerations for multisegment shared access networks describe the use of Repeaters that are defined for operational speeds up to 1000 Mb\/s. Local Area Network (LAN) operation is supported at all speeds. Other specified capabilities include various PHY types for access networks, PHYs suitable for metropolitan area network applications, and the provision of power over selected twisted-pair PHY types.<\/p>\n

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PDF Pages<\/th>\nPDF Title<\/th>\n<\/tr>\n
1<\/td>\nIEEE Std 802.3\u2122-2012, SECTION FOUR
Contents <\/td>\n<\/tr>\n
37<\/td>\n44. Introduction to 10 Gb\/s baseband network
44.1 Overview
44.1.1 Scope
44.1.2 Objectives
44.1.3 Relationship of 10 Gigabit Ethernet to the ISO OSI reference model <\/td>\n<\/tr>\n
38<\/td>\n44.1.4 Summary of 10 Gigabit Ethernet sublayers
44.1.4.1 Reconciliation Sublayer (RS) and 10 Gigabit Media Independent Interface (XGMII) <\/td>\n<\/tr>\n
39<\/td>\n44.1.4.2 XGMII Extender Sublayer (XGXS) and 10 Gigabit Attachment Unit Interface (XAUI)
44.1.4.3 Management interface (MDIO\/MDC)
44.1.4.4 Physical Layer signaling systems <\/td>\n<\/tr>\n
40<\/td>\n44.1.4.5 WAN Interface Sublayer (WIS), type 10GBASE-W
44.1.5 Management
44.2 State diagrams
44.3 Delay constraints <\/td>\n<\/tr>\n
42<\/td>\n44.4 Protocol implementation conformance statement (PICS) proforma <\/td>\n<\/tr>\n
43<\/td>\n45. Management Data Input\/Output (MDIO) Interface
45.1 Overview
45.1.1 Summary of major concepts
45.1.2 Application <\/td>\n<\/tr>\n
44<\/td>\n45.2 MDIO Interface Registers <\/td>\n<\/tr>\n
47<\/td>\n45.2.1 PMA\/PMD registers <\/td>\n<\/tr>\n
51<\/td>\n45.2.1.1 PMA\/PMD control 1 register (Register 1.0) <\/td>\n<\/tr>\n
52<\/td>\n45.2.1.1.1 Reset (1.0.15)
45.2.1.1.2 Low power (1.0.11) <\/td>\n<\/tr>\n
53<\/td>\n45.2.1.1.3 Speed selection (1.0.13,1.0.6, 1.0.5:2)
45.2.1.1.4 PMA remote loopback (1.0.1)
45.2.1.1.5 PMA local loopback (1.0.0) <\/td>\n<\/tr>\n
54<\/td>\n45.2.1.2 PMA\/PMD status 1 register (Register 1.1)
45.2.1.2.1 Fault (1.1.7)
45.2.1.2.2 Receive link status (1.1.2) <\/td>\n<\/tr>\n
55<\/td>\n45.2.1.2.3 Low-power ability (1.1.1)
45.2.1.3 PMA\/PMD device identifier (Registers 1.2 and 1.3)
45.2.1.4 PMA\/PMD speed ability (Register 1.4) <\/td>\n<\/tr>\n
56<\/td>\n45.2.1.4.1 100G capable (1.4.9)
45.2.1.4.2 40G capable (1.4.8)
45.2.1.4.3 10\/1G capable (1.4.7)
45.2.1.4.4 10M capable (1.4.6)
45.2.1.4.5 100M capable (1.4.5)
45.2.1.4.6 1000M capable (1.4.4)
45.2.1.4.7 10PASS-TS capable (1.4.2)
45.2.1.4.8 2BASE-TL capable (1.4.1) <\/td>\n<\/tr>\n
57<\/td>\n45.2.1.4.9 10G capable (1.4.0)
45.2.1.5 PMA\/PMD devices in package (Registers 1.5 and 1.6)
45.2.1.6 PMA\/PMD control 2 register (Register 1.7)
45.2.1.6.1 PMA\/PMD type selection (1.7.5:0)
45.2.1.7 PMA\/PMD status 2 register (Register 1.8)
45.2.1.7.1 Device present (1.8.15:14)
45.2.1.7.2 Transmit fault ability (1.8.13)
45.2.1.7.3 Receive fault ability (1.8.12)
45.2.1.7.4 Transmit fault (1.8.11) <\/td>\n<\/tr>\n
59<\/td>\n45.2.1.7.5 Receive fault (1.8.10) <\/td>\n<\/tr>\n
61<\/td>\n45.2.1.7.6 PMA\/PMD extended abilities (1.8.9)
45.2.1.7.7 PMD transmit disable ability (1.8.8)
45.2.1.7.8 10GBASE-SR ability (1.8.7)
45.2.1.7.9 10GBASE-LR ability (1.8.6)
45.2.1.7.10 10GBASE-ER ability (1.8.5)
45.2.1.7.11 10GBASE-LX4 ability (1.8.4) <\/td>\n<\/tr>\n
62<\/td>\n45.2.1.7.12 10GBASE-SW ability (1.8.3)
45.2.1.7.13 10GBASE-LW ability (1.8.2)
45.2.1.7.14 10GBASE-EW ability (1.8.1)
45.2.1.7.15 PMA local loopback ability (1.8.0)
45.2.1.8 PMD transmit disable register (Register 1.9)
45.2.1.8.1 PMD transmit disable 9 (1.9.10) <\/td>\n<\/tr>\n
63<\/td>\n45.2.1.8.2 PMD transmit disable 4, 5, 6, 7, 8 (1.9.5, 1.9.6, 1.9.7, 1.9.8, 1.9.9)
45.2.1.8.3 PMD transmit disable 3 (1.9.4) <\/td>\n<\/tr>\n
64<\/td>\n45.2.1.8.4 PMD transmit disable 2 (1.9.3)
45.2.1.8.5 PMD transmit disable 1 (1.9.2)
45.2.1.8.6 PMD transmit disable 0 (1.9.1)
45.2.1.8.7 Global PMD transmit disable (1.9.0)
45.2.1.9 PMD receive signal detect register (Register 1.10) <\/td>\n<\/tr>\n
65<\/td>\n45.2.1.9.1 PMD receive signal detect 9 (1.10.10)
45.2.1.9.2 PMD receive signal detect 4, 5, 6, 7, 8 (1.10.5, 1.10.6, 1.10.7, 1.10.8, 1.10.9)
45.2.1.9.3 PMD receive signal detect 3 (1.10.4) <\/td>\n<\/tr>\n
66<\/td>\n45.2.1.9.4 PMD receive signal detect 2 (1.10.3)
45.2.1.9.5 PMD receive signal detect 1 (1.10.2)
45.2.1.9.6 PMD receive signal detect 0 (1.10.1)
45.2.1.9.7 Global PMD receive signal detect (1.10.0)
45.2.1.10 PMA\/PMD extended ability register (Register 1.11) <\/td>\n<\/tr>\n
67<\/td>\n45.2.1.10.1 P2MP ability (1.11.9)
45.2.1.10.2 10BASE-T ability (1.11.8)
45.2.1.10.3 100BASE-TX ability (1.11.7)
45.2.1.10.4 1000BASE-KX ability (1.11.6)
45.2.1.10.5 1000BASE-T ability (1.11.5)
45.2.1.10.6 10GBASE-KR ability (1.11.4) <\/td>\n<\/tr>\n
68<\/td>\n45.2.1.10.7 10GBASE-KX4 ability (1.11.3)
45.2.1.10.8 10GBASE-T ability (1.11.2)
45.2.1.10.9 10GBASE-LRM ability (1.11.1)
45.2.1.10.10 10GBASE-CX4 ability (1.11.0)
45.2.1.11 10G-EPON PMA\/PMD ability register (Register 1.12) <\/td>\n<\/tr>\n
69<\/td>\n45.2.1.11.1 10\/1GBASE-PRX-D1 ability (1.12.10)
45.2.1.11.2 10\/1GBASE-PRX-D2 ability (1.12.9)
45.2.1.11.3 10\/1GBASE-PRX-D3 ability (1.12.8)
45.2.1.11.4 10GBASE-PR-D1 ability (1.12.7)
45.2.1.11.5 10GBASE-PR-D2 ability (1.12.6)
45.2.1.11.6 10GBASE-PR-D3 ability (1.12.5) <\/td>\n<\/tr>\n
70<\/td>\n45.2.1.11.7 10\/1GBASE-PRX-U1 ability (1.12.4)
45.2.1.11.8 10\/1GBASE-PRX-U2 ability (1.12.3)
45.2.1.11.9 10\/1GBASE-PRX-U3 ability (1.12.2)
45.2.1.11.10 10GBASE-PR-U1 ability (1.12.1)
45.2.1.11.11 10GBASE-PR-U3 ability (1.12.0)
45.2.1.12 40G\/100G PMA\/PMD extended ability register (Register 1.13) <\/td>\n<\/tr>\n
71<\/td>\n45.2.1.12.1 PMA remote loopback ability (1.13.15)
45.2.1.12.2 100GBASE-ER4 ability (1.13.11)
45.2.1.12.3 100GBASE-LR4 ability (1.13.10)
45.2.1.12.4 100GBASE-SR10 ability (1.13.9)
45.2.1.12.5 100GBASE-CR10 ability (1.13.8) <\/td>\n<\/tr>\n
72<\/td>\n45.2.1.12.6 40GBASE-FR ability (1.13.4)
45.2.1.12.7 40GBASE-LR4 ability (1.13.3)
45.2.1.12.8 40GBASE-SR4 ability (1.13.2)
45.2.1.12.9 40GBASE-CR4 ability (1.13.1)
45.2.1.12.10 40GBASE-KR4 ability (1.13.0)
45.2.1.13 PMA\/PMD package identifier (Registers 1.14 and 1.15)
45.2.1.14 10P\/2B PMA\/PMD control register (Register 1.30)
45.2.1.14.1 PMA\/PMD link control (1.30.15) <\/td>\n<\/tr>\n
73<\/td>\n45.2.1.14.2 STFU (1.30.14)
45.2.1.14.3 Silence time (1.30.13:8)
45.2.1.14.4 Port subtype select (1.30.7) <\/td>\n<\/tr>\n
74<\/td>\n45.2.1.14.5 Handshake cleardown (1.30.6)
45.2.1.14.6 Ignore incoming handshake (1.30.5)
45.2.1.14.7 PMA\/PMD type selection (1.30.4:0)
45.2.1.15 10P\/2B PMA\/PMD status register (Register 1.31) <\/td>\n<\/tr>\n
75<\/td>\n45.2.1.15.1 Data rate (1.31.15:5)
45.2.1.15.2 CO supported (1.31.4)
45.2.1.15.3 CPE supported (1.31.3)
45.2.1.15.4 PMA\/PMD link status (1.31.2:0)
45.2.1.16 Link partner PMA\/PMD control register (Register 1.32) <\/td>\n<\/tr>\n
77<\/td>\n45.2.1.16.1 Get link partner parameters (1.32.15)
45.2.1.16.2 Send link partner parameters (1.32.13)
45.2.1.17 Link partner PMA\/PMD status register (Register 1.33) <\/td>\n<\/tr>\n
78<\/td>\n45.2.1.17.1 Get link partner result (1.33.14)
45.2.1.17.2 Send link partner result (1.33.12)
45.2.1.18 10P\/2B PMA\/PMD link loss register (Register 1.36)
45.2.1.19 10P\/2B RX SNR margin register (Register 1.37) <\/td>\n<\/tr>\n
79<\/td>\n45.2.1.20 10P\/2B link partner RX SNR margin register (Register 1.38)
45.2.1.21 10P\/2B line attenuation register (Register 1.39)
45.2.1.22 10P\/2B link partner line attenuation register (Register 1.40)
45.2.1.23 10P\/2B line quality thresholds register (Register 1.41) <\/td>\n<\/tr>\n
80<\/td>\n45.2.1.23.1 Loop attenuation threshold (1.41.15:8)
45.2.1.23.2 SNR margin threshold (1.41.7:4)
45.2.1.24 2B link partner line quality thresholds register (Register 1.42)
45.2.1.25 10P FEC correctable errors counter (Register 1.43)
45.2.1.26 10P FEC uncorrectable errors counter (Register 1.44) <\/td>\n<\/tr>\n
81<\/td>\n45.2.1.27 10P link partner FEC correctable errors register (Register 1.45)
45.2.1.28 10P link partner FEC uncorrectable errors register (Register 1.46)
45.2.1.29 10P electrical length register (Register 1.47)
45.2.1.29.1 Electrical length (1.47.15:0)
45.2.1.30 10P link partner electrical length register (Register 1.48) <\/td>\n<\/tr>\n
82<\/td>\n45.2.1.31 10P PMA\/PMD general configuration register (Register 1.49)
45.2.1.31.1 TX window length (1.49.7:0)
45.2.1.32 10P PSD configuration register (Register 1.50)
45.2.1.32.1 PBO disable (1.50.8)
45.2.1.33 10P downstream data rate configuration (Registers 1.51, 1.52) <\/td>\n<\/tr>\n
83<\/td>\n45.2.1.34 10P downstream Reed-Solomon configuration (Register 1.53)
45.2.1.34.1 RS codeword length (1.53.0)
45.2.1.35 10P upstream data rate configuration (Registers 1.54, 1.55)
45.2.1.36 10P upstream 10P upstream Reed-Solomon configuration register (Register 1.56) <\/td>\n<\/tr>\n
84<\/td>\n45.2.1.36.1 RS codeword length (1.56.0)
45.2.1.37 10P tone group registers (Registers 1.57, 1.58) <\/td>\n<\/tr>\n
85<\/td>\n45.2.1.38 10P tone control parameters (Registers 1.59, 1.60, 1.61, 1.62, 1.63)
45.2.1.38.1 Tone active (1.59.15)
45.2.1.38.2 Tone direction (1.59.14) <\/td>\n<\/tr>\n
86<\/td>\n45.2.1.38.3 Max SNR margin (1.59.13:5)
45.2.1.38.4 Target SNR margin (1.60.8:0)
45.2.1.38.5 Minimum SNR margin (1.61.8:0)
45.2.1.38.6 PSD level (1.62.8:0)
45.2.1.38.7 USPBO reference (1.63.8:0)
45.2.1.39 10P tone control action register (Register 1.64) <\/td>\n<\/tr>\n
87<\/td>\n45.2.1.39.1 Refresh tone status (1.64.5)
45.2.1.39.2 Change tone activity (1.64.4)
45.2.1.39.3 Change tone direction (1.64.3)
45.2.1.39.4 Change SNR margin (1.64.2)
45.2.1.39.5 Change PSD level (1.64.1) <\/td>\n<\/tr>\n
88<\/td>\n45.2.1.39.6 Change USPBO reference PSD (1.64.0)
45.2.1.40 10P tone status registers (Registers 1.65, 1.66, 1.67)
45.2.1.40.1 Refresh status (1.65.15)
45.2.1.40.2 Active (1.65.14) <\/td>\n<\/tr>\n
89<\/td>\n45.2.1.40.3 Direction (1.65.13)
45.2.1.40.4 RX PSD (1.65.7:0)
45.2.1.40.5 TX PSD (1.66.15:8)
45.2.1.40.6 Bit load (1.66.7:3)
45.2.1.40.7 SNR margin (1.67.9:0)
45.2.1.41 10P outgoing indicator bits status register (Register 1.68) <\/td>\n<\/tr>\n
90<\/td>\n45.2.1.41.1 LoM (1.68.8)
45.2.1.41.2 lpr (1.68.7)
45.2.1.41.3 po (1.68.6)
45.2.1.41.4 Rdi (1.68.5)
45.2.1.41.5 los (1.68.4)
45.2.1.41.6 fec-s (1.68.1)
45.2.1.41.7 be-s (1.68.0)
45.2.1.42 10P incoming indicator bits status register (Register 1.69) <\/td>\n<\/tr>\n
91<\/td>\n45.2.1.42.1 LoM (1.69.8)
45.2.1.42.2 Flpr (1.69.7)
45.2.1.42.3 Fpo (1.69.6)
45.2.1.42.4 Rdi (1.69.5) <\/td>\n<\/tr>\n
92<\/td>\n45.2.1.42.5 Flos (1.69.4)
45.2.1.42.6 Ffec-s (1.69.1)
45.2.1.42.7 Febe-s (1.69.0)
45.2.1.43 10P cyclic extension configuration register (Register 1.70)
45.2.1.44 10P attainable downstream data rate register (Register 1.71) <\/td>\n<\/tr>\n
93<\/td>\n45.2.1.45 2B general parameter register (Register 1.80)
45.2.1.45.1 PMMS target margin (1.80.14:10)
45.2.1.45.2 Line probing control (1.80.9) <\/td>\n<\/tr>\n
94<\/td>\n45.2.1.45.3 Noise environment (1.80.8)
45.2.1.45.4 Region (1.80.1:0)
45.2.1.46 2B PMD parameters registers (Registers 1.81 through 1.88) <\/td>\n<\/tr>\n
96<\/td>\n45.2.1.46.1 Minimum data rate (1.81, 1.83, 1.85, 1.87. Bits 14:8)
45.2.1.46.2 Max data rate (1.81, 1.83, 1.85, 1.87. Bits 6:0) <\/td>\n<\/tr>\n
97<\/td>\n45.2.1.46.3 Data rate step (1.82, 1.84, 1.86, 1.88. Bits 13:7)
45.2.1.46.4 Power (1.82, 1.84, 1.86, 1.88. Bits 6:2)
45.2.1.46.5 Constellation (1.82, 1.84, 1.86, 1.88. Bits 1:0)
45.2.1.47 2B code violation errors counter (Register 1.89)
45.2.1.48 2B link partner code violations register (Register 1.90) <\/td>\n<\/tr>\n
98<\/td>\n45.2.1.49 2B errored seconds counter (Register 1.91)
45.2.1.50 2B link partner errored seconds register (Register 1.92)
45.2.1.51 2B severely errored seconds counter (Register 1.93)
45.2.1.52 2B link partner severely errored seconds register (Register 1.94) <\/td>\n<\/tr>\n
99<\/td>\n45.2.1.53 2B LOSW counter (Register 1.95)
45.2.1.54 2B link partner LOSW register (Register 1.96)
45.2.1.55 2B unavailable seconds counter (Register 1.97) <\/td>\n<\/tr>\n
100<\/td>\n45.2.1.56 2B link partner unavailable seconds register (Register 1.98)
45.2.1.57 2B state defects register (Register 1.99)
45.2.1.57.1 Segment defect (1.99.15)
45.2.1.57.2 SNR margin defect (1.99.14)
45.2.1.57.3 Loop attenuation defect (1.99.13) <\/td>\n<\/tr>\n
101<\/td>\n45.2.1.57.4 Loss of sync word (1.99.12)
45.2.1.58 2B link partner state defects register (Register 1.100)
45.2.1.59 2B negotiated constellation register (Register 1.101)
45.2.1.59.1 Negotiated constellation (1.101.1:0)
45.2.1.60 2B extended PMD parameters registers (Registers 1.102 through 1.109) <\/td>\n<\/tr>\n
103<\/td>\n45.2.1.60.1 Minimum data rate (1.102, 1.104, 1.106, 1.108. Bits 14:8)
45.2.1.60.2 Max data rate (1.102, 1.104, 1.106, 1.108. Bits 6:0) <\/td>\n<\/tr>\n
104<\/td>\n45.2.1.60.3 Data rate step (1.103, 1.105, 1.107, 1.109. Bits 13:7)
45.2.1.60.4 Power (1.103, 1.105, 1.107, 1.109. Bits 6:2)
45.2.1.60.5 Constellation (1.103, 1.105, 1.107, 1.109. Bits 1:0)
45.2.1.61 10GBASE-T status (Register 1.129)
45.2.1.61.1 LP information valid (1.129.0)
45.2.1.62 10GBASE-T pair swap and polarity register (Register 1.130) <\/td>\n<\/tr>\n
105<\/td>\n45.2.1.62.1 Pair D polarity (1.130.11)
45.2.1.62.2 Pair C polarity (1.130.10)
45.2.1.62.3 Pair B polarity (1.130.9)
45.2.1.62.4 Pair A polarity (1.130.8)
45.2.1.62.5 MDI\/MDI-X connection (1.130.1:0)
45.2.1.63 10GBASE-T TX power backoff and PHY short reach setting (Register 1.131) <\/td>\n<\/tr>\n
106<\/td>\n45.2.1.63.1 10GBASE-T TX power backoff settings (1.131.15:10)
45.2.1.63.2 PHY short reach mode (1.131.0)
45.2.1.64 10GBASE-T test mode register (Register 1.132) <\/td>\n<\/tr>\n
107<\/td>\n45.2.1.64.1 Test mode control (1.132.15:13)
45.2.1.64.2 Transmitter test frequencies (1.132.12:10)
45.2.1.65 SNR operating margin channel A register (Register 1.133)
45.2.1.66 SNR operating margin channel B register (Register 1.134) <\/td>\n<\/tr>\n
108<\/td>\n45.2.1.67 SNR operating margin channel C register (Register 1.135)
45.2.1.68 SNR operating margin channel D register (Register 1.136)
45.2.1.69 Minimum margin channel A register (Register 1.137)
45.2.1.70 Minimum margin channel B register (Register 1.138)
45.2.1.71 Minimum margin channel C register (Register 1.139)
45.2.1.72 Minimum margin channel D register (Register 1.140)
45.2.1.73 RX signal power channel A register (Register 1.141) <\/td>\n<\/tr>\n
109<\/td>\n45.2.1.74 RX signal power channel B register (Register 1.142)
45.2.1.75 RX signal power channel C register (Register 1.143)
45.2.1.76 RX signal power channel D register (Register 1.144)
45.2.1.77 10GBASE-T skew delay register (Registers 1.145 and 1.146) <\/td>\n<\/tr>\n
110<\/td>\n45.2.1.78 10GBASE-T fast retrain status and control register (Register 1.147)
45.2.1.78.1 LP fast retrain count (1.147.15:11)
45.2.1.78.2 LD fast retrain count (1.147.10:6)
45.2.1.78.3 Fast retrain ability (1.147.4)
45.2.1.78.4 Fast retrain negotiated (1.147.3) <\/td>\n<\/tr>\n
111<\/td>\n45.2.1.78.5 Fast retrain signal type (1.147.2:1)
45.2.1.78.6 Fast retrain enable (1.147.0)
45.2.1.79 BASE-R PMD control register (Register 1.150)
45.2.1.79.1 Restart training (1.150.0)
45.2.1.79.2 Training enable (1.150.1)
45.2.1.80 BASE-R PMD status register (Register 1.151) <\/td>\n<\/tr>\n
112<\/td>\n45.2.1.80.1 Receiver status 0 (1.151.0) <\/td>\n<\/tr>\n
113<\/td>\n45.2.1.80.2 Frame lock 0 (1.151.1)
45.2.1.80.3 Start-up protocol status 0 (1.151.2)
45.2.1.80.4 Training failure 0 (1.151.3)
45.2.1.80.5 Receiver status 1, 2, 3 (1.151.4, 1.151.8, 1.151.12)
45.2.1.80.6 Frame lock 1, 2, 3 (1.151.5, 1.151.9, 1.151.13)
45.2.1.80.7 Start-up protocol status 1, 2, 3 (1.151.6, 1.151.10, 1.151.14)
45.2.1.80.8 Training failure 1, 2, 3 (1.151.7, 1.151.11, 1.151.15)
45.2.1.81 BASE-R LP coefficient update, lane 0 register (Register 1.152)
45.2.1.81.1 Preset (1.152.13)
45.2.1.81.2 Initialize (1.152.12) <\/td>\n<\/tr>\n
114<\/td>\n45.2.1.81.3 Coefficient (k) update (1.152.5:0)
45.2.1.82 BASE-R LP status report, lane 0 register (Register 1.153) <\/td>\n<\/tr>\n
115<\/td>\n45.2.1.82.1 Receiver ready (1.153.15)
45.2.1.82.2 Coefficient (k) status (1.153.5:0)
45.2.1.83 BASE-R LD coefficient update, lane 0 register (Register 1.154)
45.2.1.83.1 Preset (1.154.13) <\/td>\n<\/tr>\n
116<\/td>\n45.2.1.83.2 Initialize (1.154.12)
45.2.1.83.3 Coefficient (k) update(1.154.5:0)
45.2.1.84 BASE-R LD status report, lane 0 register (Register 1.155)
45.2.1.84.1 Receiver ready (1.155.15) <\/td>\n<\/tr>\n
117<\/td>\n45.2.1.84.2 Coefficient (k) status (1.155.5:0)
45.2.1.85 BASE-R PMD status 2 register (Register 1.156) <\/td>\n<\/tr>\n
118<\/td>\n45.2.1.85.1 Receiver status 4, 5, 6, 7 (1.156.0, 1.156.4, 1.156.8, 1.156.12)
45.2.1.85.2 Frame lock 4, 5, 6, 7 (1.156.1, 1.156.5, 1.156.9, 1.156.13)
45.2.1.85.3 Start-up protocol status 4, 5, 6, 7 (1.156.2, 1.156.6, 1.156.10, 1.156.14)
45.2.1.85.4 Training failure 4, 5, 6, 7 (1.156.3, 1.156.7, 1.156.11, 1.156.15)
45.2.1.86 BASE-R PMD status 3 register (Register 1.157) <\/td>\n<\/tr>\n
119<\/td>\n45.2.1.86.1 Receiver status 8, 9 (1.157.0, 1.157.4)
45.2.1.86.2 Frame lock 8, 9 (1.157.1, 1.157.5)
45.2.1.86.3 Start-up protocol status 8, 9 (1.157.2, 1.157.6)
45.2.1.86.4 Training failure 8, 9 (1.157.3, 1.157.7) <\/td>\n<\/tr>\n
120<\/td>\n45.2.1.87 1000BASE-KX control register (Register 1.160)
45.2.1.87.1 PMD transmit disable (1.160.0) <\/td>\n<\/tr>\n
121<\/td>\n45.2.1.88 1000BASE-KX status register (Register 1.161)
45.2.1.88.1 PMD transmit fault ability (1.161.13)
45.2.1.88.2 PMD receive fault ability (1.161.12)
45.2.1.88.3 PMD transmit fault (1.161.11) <\/td>\n<\/tr>\n
122<\/td>\n45.2.1.88.4 PMD receive fault (1.161.10)
45.2.1.88.5 PMD transmit disable ability (1.161.8)
45.2.1.88.6 1000BASE-KX signal detect (1.161.0)
45.2.1.89 BASE-R FEC ability register (Register 1.170)
45.2.1.89.1 BASE-R FEC ability (1.170.0)
45.2.1.89.2 BASE-R FEC error indication ability (1.170.1) <\/td>\n<\/tr>\n
123<\/td>\n45.2.1.90 BASE-R FEC control register (Register 1.171)
45.2.1.90.1 FEC enable (1.171.0)
45.2.1.90.2 FEC enable error indication (1.171.1)
45.2.1.91 10GBASE-R FEC corrected blocks counter (Register 1.172, 1.173) <\/td>\n<\/tr>\n
124<\/td>\n45.2.1.92 10GBASE-R FEC uncorrected blocks counter (Register 1.174, 1.175)
45.2.1.93 BASE-R FEC corrected blocks counter, lanes 0 through 19
45.2.1.94 BASE-R FEC uncorrected blocks counter, lanes 0 through 19 <\/td>\n<\/tr>\n
125<\/td>\n45.2.1.95 BASE-R LP coefficient update register, lanes 1 through 9
45.2.1.96 BASE-R LP status report register, lanes 1 through 9
45.2.1.97 BASE-R LD coefficient update register, lanes 1 through 9
45.2.1.98 BASE-R LD status report register, lanes 1 through 9
45.2.1.99 Test-pattern ability (Register 1.1500) <\/td>\n<\/tr>\n
126<\/td>\n45.2.1.100 PRBS pattern testing control (Register 1.1501) <\/td>\n<\/tr>\n
127<\/td>\n45.2.1.101 Square wave testing control (Register 1.1510) <\/td>\n<\/tr>\n
128<\/td>\n45.2.1.102 PRBS Tx pattern testing error counter (Register 1.1600, 1.1601, 1.1602, 1.1603, 1.1604, 1.1605, 1.1606, 1.1607, 1.1608, 1.1609)
45.2.1.103 PRBS Rx pattern testing error counter (Register 1.1700, 1.1701, 1.1702, 1.1703, 1.1704, 1.1705, 1.1706, 1.1707, 1.1708, 1.1709) <\/td>\n<\/tr>\n
129<\/td>\n45.2.1.104 TimeSync PMA\/PMD capability (Register 1.1800)
45.2.1.105 TimeSync PMA\/PMD transmit path data delay (Registers 1.1801, 1.1802, 1.1803, 1.1804) <\/td>\n<\/tr>\n
130<\/td>\n45.2.1.106 TimeSync PMA\/PMD receive path data delay (Registers 1.1805, 1.1806, 1.1807, 1.1808)
45.2.2 WIS registers <\/td>\n<\/tr>\n
131<\/td>\n45.2.2.1 WIS control 1 register (Register 2.0)
45.2.2.1.1 Reset (2.0.15) <\/td>\n<\/tr>\n
132<\/td>\n45.2.2.1.2 Loopback (2.0.14) <\/td>\n<\/tr>\n
133<\/td>\n45.2.2.1.3 Low power (2.0.11)
45.2.2.1.4 Speed selection (2.0.13, 2.0.6, and 2.0.5:2)
45.2.2.2 WIS status 1 register (Register 2.1)
45.2.2.2.1 Fault (2.1.7) <\/td>\n<\/tr>\n
134<\/td>\n45.2.2.2.2 Link status (2.1.2)
45.2.2.2.3 Low-power ability (2.1.1)
45.2.2.3 WIS device identifier (Registers 2.2 and 2.3)
45.2.2.4 WIS speed ability (Register 2.4)
45.2.2.4.1 10G capable (2.4.0)
45.2.2.5 WIS devices in package (Registers 2.5 and 2.6)
45.2.2.6 10G WIS control 2 register (Register 2.7) <\/td>\n<\/tr>\n
135<\/td>\n45.2.2.6.1 PRBS31 receive test-pattern enable (2.7.5)
45.2.2.6.2 PRBS31 transmit test-pattern enable (2.7.4)
45.2.2.6.3 Test-pattern selection (2.7.3)
45.2.2.6.4 Receive test-pattern enable (2.7.2) <\/td>\n<\/tr>\n
136<\/td>\n45.2.2.6.5 Transmit test-pattern enable (2.7.1)
45.2.2.6.6 PCS type selection (2.7.0)
45.2.2.7 10G WIS status 2 register (Register 2.8)
45.2.2.7.1 Device present (2.8.15:14)
45.2.2.7.2 PRBS31 pattern testing ability (2.8.1) <\/td>\n<\/tr>\n
137<\/td>\n45.2.2.7.3 10GBASE-R ability (2.8.0)
45.2.2.8 10G WIS test-pattern error counter register (Register 2.9)
45.2.2.9 WIS package identifier (Registers 2.14 and 2.15)
45.2.2.10 10G WIS status 3 register (Register 2.33)
45.2.2.10.1 SEF (2.33.11) <\/td>\n<\/tr>\n
138<\/td>\n45.2.2.10.2 Far end PLM-P\/LCD-P (2.33.10) <\/td>\n<\/tr>\n
139<\/td>\n45.2.2.10.3 Far end AIS-P\/LOP-P (2.33.9)
45.2.2.10.4 LOF (2.33.7)
45.2.2.10.5 LOS (2.33.6)
45.2.2.10.6 RDI-L (2.33.5)
45.2.2.10.7 AIS-L (2.33.4)
45.2.2.10.8 LCD-P (2.33.3) <\/td>\n<\/tr>\n
140<\/td>\n45.2.2.10.9 PLM-P (2.33.2)
45.2.2.10.10 AIS-P (2.33.1)
45.2.2.10.11 LOP-P (2.33.0)
45.2.2.11 10G WIS far end path block error count (Register 2.37)
45.2.2.12 10G WIS J1 transmit (Registers 2.39 through 2.46) <\/td>\n<\/tr>\n
141<\/td>\n45.2.2.13 10G WIS J1 receive (Registers 2.47 through 2.54) <\/td>\n<\/tr>\n
142<\/td>\n45.2.2.14 10G WIS far end line BIP errors (Registers 2.55 and 2.56) <\/td>\n<\/tr>\n
143<\/td>\n45.2.2.15 10G WIS line BIP errors (Registers 2.57 and 2.58)
45.2.2.16 10G WIS path block error count (Register 2.59)
45.2.2.16.1 Path block error count (2.59.15:0)
45.2.2.17 10G WIS section BIP error count (Register 2.60) <\/td>\n<\/tr>\n
144<\/td>\n45.2.2.17.1 Section BIP error count (2.60.15:0)
45.2.2.18 10G WIS J0 transmit (Registers 2.64 through 2.71) <\/td>\n<\/tr>\n
145<\/td>\n45.2.2.19 10G WIS J0 receive (Registers 2.72 through 2.79) <\/td>\n<\/tr>\n
146<\/td>\n45.2.2.20 TimeSync WIS capability (Register 2.1800)
45.2.2.21 TimeSync WIS transmit path data delay (Registers 2.1801, 2.1802, 2.1803, 2.1804)
45.2.2.22 TimeSync WIS receive path data delay (Registers 2.1805, 2.1806, 2.1807, 2.1808) <\/td>\n<\/tr>\n
148<\/td>\n45.2.3 PCS registers <\/td>\n<\/tr>\n
149<\/td>\n45.2.3.1 PCS control 1 register (Register 3.0) <\/td>\n<\/tr>\n
150<\/td>\n45.2.3.1.1 Reset (3.0.15)
45.2.3.1.2 Loopback (3.0.14) <\/td>\n<\/tr>\n
151<\/td>\n45.2.3.1.3 Low power (3.0.11)
45.2.3.1.4 Clock stop enable (3.0.10)
45.2.3.1.5 Speed selection (3.0.13, 3.0.6, 3.0.5:2)
45.2.3.2 PCS status 1 register (Register 3.1) <\/td>\n<\/tr>\n
152<\/td>\n45.2.3.2.1 Transmit LPI received (3.1.11)
45.2.3.2.2 Receive LPI received (3.1.10)
45.2.3.2.3 Transmit LPI indication (3.1.9)
45.2.3.2.4 Receive LPI indication (3.1.8) <\/td>\n<\/tr>\n
153<\/td>\n45.2.3.2.5 Fault (3.1.7)
45.2.3.2.6 Clock stop capable (3.1.6)
45.2.3.2.7 PCS receive link status (3.1.2)
45.2.3.2.8 Low-power ability (3.1.1)
45.2.3.3 PCS device identifier (Registers 3.2 and 3.3)
45.2.3.4 PCS speed ability (Register 3.4) <\/td>\n<\/tr>\n
154<\/td>\n45.2.3.4.1 10G capable (3.4.0)
45.2.3.4.2 10PASS-TS\/2BASE-TL capable
45.2.3.4.3 40G capable (3.4.2)
45.2.3.4.4 100G capable (3.4.3)
45.2.3.5 PCS devices in package (Registers 3.5 and 3.6)
45.2.3.6 PCS control 2 register (Register 3.7)
45.2.3.6.1 PCS type selection (3.7.2:0)
45.2.3.7 PCS status 2 register (Register 3.8) <\/td>\n<\/tr>\n
156<\/td>\n45.2.3.7.1 Device present (3.8.15:14)
45.2.3.7.2 Transmit fault (3.8.11)
45.2.3.7.3 Receive fault (3.8.10)
45.2.3.7.4 100GBASE-R capable (3.8.5)
45.2.3.7.5 40GBASE-R capable (3.8.4)
45.2.3.7.6 10GBASE-T capable (3.8.3)
45.2.3.7.7 10GBASE-W capable (3.8.2)
45.2.3.7.8 10GBASE-X capable (3.8.1) <\/td>\n<\/tr>\n
157<\/td>\n45.2.3.7.9 10GBASE-R capable (3.8.0)
45.2.3.8 PCS package identifier (Registers 3.14 and 3.15)
45.2.3.9 EEE capability (Register 3.20)
45.2.3.9.1 10GBASE-KR EEE supported (3.20.6) <\/td>\n<\/tr>\n
158<\/td>\n45.2.3.9.2 10GBASE-KX4 EEE supported (3.20.5)
45.2.3.9.3 1000BASE-KX EEE supported (3.20.4)
45.2.3.9.4 10GBASE-T EEE supported (3.20.3)
45.2.3.9.5 1000BASE-T EEE supported (3.20.2)
45.2.3.9.6 100BASE-TX EEE supported (3.20.1)
45.2.3.10 EEE wake error counter (Register 3.22)
45.2.3.11 10GBASE-X PCS status register (Register 3.24) <\/td>\n<\/tr>\n
159<\/td>\n45.2.3.11.1 10GBASE-X receive lane alignment status (3.24.12)
45.2.3.11.2 Pattern testing ability (3.24.11)
45.2.3.11.3 Lane 3 sync (3.24.3)
45.2.3.11.4 Lane 2 sync (3.24.2)
45.2.3.11.5 Lane 1 sync (3.24.1)
45.2.3.11.6 Lane 0 sync (3.24.0)
45.2.3.12 10GBASE-X PCS test control register (Register 3.25) <\/td>\n<\/tr>\n
160<\/td>\n45.2.3.12.1 Transmit test-pattern enable (3.25.2)
45.2.3.12.2 Test pattern select (3.25.1:0)
45.2.3.13 BASE-R and 10GBASE-T PCS status 1 register (Register 3.32) <\/td>\n<\/tr>\n
161<\/td>\n45.2.3.13.1 BASE-R and 10GBASE-T receive link status (3.32.12)
45.2.3.13.2 PRBS9 pattern testing ability (3.32.3)
45.2.3.13.3 PRBS31 pattern testing ability (3.32.2)
45.2.3.13.4 BASE-R and 10GBASE-T PCS high BER (3.32.1) <\/td>\n<\/tr>\n
162<\/td>\n45.2.3.13.5 BASE-R and 10GBASE-T PCS block lock (3.32.0)
45.2.3.14 BASE-R and 10GBASE-T PCS status 2 register (Register 3.33)
45.2.3.14.1 Latched block lock (3.33.15)
45.2.3.14.2 Latched high BER (3.33.14) <\/td>\n<\/tr>\n
163<\/td>\n45.2.3.14.3 BER(3.33.13:8)
45.2.3.14.4 Errored blocks (3.33.7:0)
45.2.3.15 10GBASE-R PCS test pattern seed A (Registers 3.34 through 3.37)
45.2.3.16 10GBASE-R PCS test pattern seed B (Registers 3.38 through 3.41) <\/td>\n<\/tr>\n
164<\/td>\n45.2.3.17 BASE-R PCS test-pattern control register (Register 3.42) <\/td>\n<\/tr>\n
165<\/td>\n45.2.3.17.1 Scrambled idle test-pattern enable (3.42.7)
45.2.3.17.2 10GBASE-R PRBS9 transmit test-pattern enable (3.42.6)
45.2.3.17.3 10GBASE-R PRBS31 receive test-pattern enable (3.42.5)
45.2.3.17.4 10GBASE-R PRBS31 transmit test-pattern enable (3.42.4)
45.2.3.17.5 Transmit test-pattern enable (3.42.3) <\/td>\n<\/tr>\n
166<\/td>\n45.2.3.17.6 Receive test-pattern enable (3.42.2)
45.2.3.17.7 Test-pattern select (3.42.1)
45.2.3.17.8 Data pattern select (3.42.0)
45.2.3.18 BASE-R PCS test-pattern error counter register (Register 3.43)
45.2.3.19 BER high order counter (Register 3.44) <\/td>\n<\/tr>\n
167<\/td>\n45.2.3.20 Errored blocks high order counter (Register 3.45)
45.2.3.21 Multi-lane BASE-R PCS alignment status 1 register (Register 3.50)
45.2.3.21.1 Multi-lane BASE-R PCS alignment status (3.50.12) <\/td>\n<\/tr>\n
168<\/td>\n45.2.3.21.2 Block 7 lock (3.50.7)
45.2.3.21.3 Block 6 lock (3.50.6)
45.2.3.21.4 Block 5 lock (3.50.5) <\/td>\n<\/tr>\n
169<\/td>\n45.2.3.21.5 Block 4 lock (3.50.4)
45.2.3.21.6 Block 3 lock (3.50.3)
45.2.3.21.7 Block 2 lock (3.50.2)
45.2.3.21.8 Block 1 lock (3.50.1)
45.2.3.21.9 Block 0 lock (3.50.0)
45.2.3.22 Multi-lane BASE-R PCS alignment status 2 register (Register 3.51) <\/td>\n<\/tr>\n
170<\/td>\n45.2.3.22.1 Block 19 lock (3.51.11)
45.2.3.22.2 Block 18 lock (3.51.10)
45.2.3.22.3 Block 17 lock (3.51.9) <\/td>\n<\/tr>\n
171<\/td>\n45.2.3.22.4 Block 16 lock (3.51.8)
45.2.3.22.5 Block 15 lock (3.51.7)
45.2.3.22.6 Block 14 lock (3.51.6)
45.2.3.22.7 Block 13 lock (3.51.5)
45.2.3.22.8 Block 12 lock (3.51.4)
45.2.3.22.9 Block 11 lock (3.51.3)
45.2.3.22.10 Block 10 lock (3.51.2)
45.2.3.22.11 Block 9 lock (3.51.1)
45.2.3.22.12 Block 8 lock (3.51.0) <\/td>\n<\/tr>\n
172<\/td>\n45.2.3.23 Multi-lane BASE-R PCS alignment status 3 register (Register 3.52)
45.2.3.23.1 Lane 7 aligned (3.52.7)
45.2.3.23.2 Lane 6 aligned (3.52.6) <\/td>\n<\/tr>\n
173<\/td>\n45.2.3.23.3 Lane 5 aligned (3.52.5)
45.2.3.23.4 Lane 4 aligned (3.52.4)
45.2.3.23.5 Lane 3 aligned (3.52.3)
45.2.3.23.6 Lane 2 aligned (3.52.2)
45.2.3.23.7 Lane 1 aligned (3.52.1)
45.2.3.23.8 Lane 0 aligned (3.52.0)
45.2.3.24 Multi-lane BASE-R PCS alignment status 4 register (Register 3.53)
45.2.3.24.1 Lane 19 aligned (3.53.11) <\/td>\n<\/tr>\n
174<\/td>\n45.2.3.24.2 Lane 18 aligned (3.53.10)
45.2.3.24.3 Lane 17 aligned (3.53.9) <\/td>\n<\/tr>\n
175<\/td>\n45.2.3.24.4 Lane 16 aligned (3.53.8)
45.2.3.24.5 Lane 15 aligned (3.53.7)
45.2.3.24.6 Lane 14 aligned (3.53.6)
45.2.3.24.7 Lane 13 aligned (3.53.5)
45.2.3.24.8 Lane 12 aligned (3.53.4)
45.2.3.24.9 Lane 11 aligned (3.53.3)
45.2.3.24.10 Lane 10 aligned (3.53.2)
45.2.3.24.11 Lane 9 aligned (3.53.1)
45.2.3.24.12 Lane 8 aligned (3.53.0) <\/td>\n<\/tr>\n
176<\/td>\n45.2.3.25 10P\/2B capability register (3.60)
45.2.3.25.1 PAF available (3.60.12)
45.2.3.25.2 Remote PAF supported (3.60.11)
45.2.3.26 10P\/2B PCS control register (Register 3.61) <\/td>\n<\/tr>\n
177<\/td>\n45.2.3.26.1 MII receive during transmit (3.61.15)
45.2.3.26.2 TX_EN and CRS infer a collision (3.61.14)
45.2.3.26.3 PAF enable (3.61.0)
45.2.3.27 10P\/2B PME available (Registers 3.62 and 3.63) <\/td>\n<\/tr>\n
178<\/td>\n45.2.3.28 10P\/2B PME aggregate registers (Registers 3.64 and 3.65)
45.2.3.29 10P\/2B PAF RX error register (Register 3.66) <\/td>\n<\/tr>\n
179<\/td>\n45.2.3.30 10P\/2B PAF small fragments register (Register 3.67)
45.2.3.31 10P\/2B PAF large fragments register (Register 3.68) <\/td>\n<\/tr>\n
180<\/td>\n45.2.3.32 10P\/2B PAF overflow register (Register 3.69)
45.2.3.33 10P\/2B PAF bad fragments register (Register 3.70)
45.2.3.34 10P\/2B PAF lost fragments register (Register 3.71) <\/td>\n<\/tr>\n
181<\/td>\n45.2.3.35 10P\/2B PAF lost starts of fragments register (Register 3.72)
45.2.3.36 10P\/2B PAF lost ends of fragments register (Register 3.73)
45.2.3.37 10GBASE-PR and 10\/1GBASE-PRX FEC ability register (Register 3.74) <\/td>\n<\/tr>\n
182<\/td>\n45.2.3.38 10GBASE-PR and 10\/1GBASE-PRX FEC control register (Register 3.75)
45.2.3.38.1 FEC enable error indication (3.75.1)
45.2.3.38.2 10 Gb\/s FEC Enable (3.75.0)
45.2.3.39 10\/1GBASE-PRX and 10GBASE-PR corrected FEC codewords counter (Register 3.76, 3.77) <\/td>\n<\/tr>\n
183<\/td>\n45.2.3.40 10\/1GBASE-PRX and 10GBASE-PR uncorrected FEC codewords counter (Register 3.78, 3.79)
45.2.3.41 10GBASE-PR and 10\/1GBASE-PRX BER monitor timer control register (Register 3.80) <\/td>\n<\/tr>\n
184<\/td>\n45.2.3.42 10GBASE-PR and 10\/1GBASE-PRX BER monitor status (Register 3.81)
45.2.3.42.1 10GBASE-PR and 10\/1GBASE-PRX PCS high BER (3.81.0)
45.2.3.42.2 10GBASE-PR and 10\/1GBASE-PRX PCS latched high BER (3.81.1)
45.2.3.43 10GBASE-PR and 10\/1GBASE-PRX BER monitor threshold control (Register 3.82) <\/td>\n<\/tr>\n
185<\/td>\n45.2.3.44 BIP error counter lane 0 (Register 3.200)
45.2.3.45 BIP error counter, lanes 1 through 19 (Registers 3.201 through 3.219)
45.2.3.46 Lane 0 mapping register (Register 3.400)
45.2.3.47 Lanes 1 through 19 mapping registers (Registers 3.401 through 3.419) <\/td>\n<\/tr>\n
186<\/td>\n45.2.3.48 TimeSync PCS capability (Register 3.1800)
45.2.3.49 TimeSync PCS transmit path data delay (Registers 3.1801, 3.1802, 3.1803, 3.1804)
45.2.3.50 TimeSync PCS receive path data delay (Registers 3.1805, 3.1806, 3.1807, 3.1808) <\/td>\n<\/tr>\n
187<\/td>\n45.2.4 PHY XS registers <\/td>\n<\/tr>\n
188<\/td>\n45.2.4.1 PHY XS control 1 register (Register 4.0) <\/td>\n<\/tr>\n
189<\/td>\n45.2.4.1.1 Reset (4.0.15)
45.2.4.1.2 Loopback (4.0.14)
45.2.4.1.3 Low power (4.0.11)
45.2.4.1.4 Clock stop enable (4.0.10)
45.2.4.1.5 XAUI stop enable (4.0.9) <\/td>\n<\/tr>\n
190<\/td>\n45.2.4.1.6 Speed selection (4.0.13, 4.0.6, 4.0.5:2)
45.2.4.2 PHY XS status 1 register (Register 4.1) <\/td>\n<\/tr>\n
191<\/td>\n45.2.4.2.1 Transmit LPI received (4.1.11)
45.2.4.2.2 Receive LPI received (4.1.10)
45.2.4.2.3 Transmit LPI indication (4.1.9)
45.2.4.2.4 Receive LPI indication (4.1.8)
45.2.4.2.5 Fault (4.1.7)
45.2.4.2.6 Clock stop capable (4.1.6)
45.2.4.2.7 PHY XS transmit link status (4.1.2)
45.2.4.2.8 Low-power ability (4.1.1) <\/td>\n<\/tr>\n
192<\/td>\n45.2.4.3 PHY XS device identifier (Registers 4.2 and 4.3)
45.2.4.4 PHY XS speed ability (Register 4.4)
45.2.4.4.1 10G capable (4.4.0)
45.2.4.5 PHY XS devices in package (Registers 4.5 and 4.6)
45.2.4.6 PHY XS status 2 register (Register 4.8) <\/td>\n<\/tr>\n
193<\/td>\n45.2.4.6.1 Device present (4.8.15:14)
45.2.4.6.2 Transmit fault (4.8.11)
45.2.4.6.3 Receive fault (4.8.10)
45.2.4.7 PHY XS package identifier (Registers 4.14 and 4.15) <\/td>\n<\/tr>\n
194<\/td>\n45.2.4.8 EEE capability (Register 4.20)
45.2.4.8.1 PHY XS EEE supported (4.20.4)
45.2.4.8.2 XAUI stop capable (4.20.0)
45.2.4.9 EEE wake error counter (Register 4.22)
45.2.4.10 10G PHY XGXS lane status register (Register 4.24)
45.2.4.10.1 PHY XGXS transmit lane alignment status (4.24.12) <\/td>\n<\/tr>\n
195<\/td>\n45.2.4.10.2 Pattern testing ability (4.24.11)
45.2.4.10.3 PHY XS loopback ability (4.24.10)
45.2.4.10.4 Lane 3 sync (4.24.3)
45.2.4.10.5 Lane 2 sync (4.24.2) <\/td>\n<\/tr>\n
196<\/td>\n45.2.4.10.6 Lane 1 sync (4.24.1)
45.2.4.10.7 Lane 0 sync (4.24.0)
45.2.4.11 10G PHY XGXS test control register (Register 4.25)
45.2.4.11.1 10G PHY XGXS test-pattern enable (4.25.2)
45.2.4.11.2 10G PHY XGXS test-pattern select (4.25.1:0) <\/td>\n<\/tr>\n
197<\/td>\n45.2.4.12 TimeSync PHY XS capability (Register 4.1800)
45.2.4.13 TimeSync PHY XS transmit path data delay (Registers 4.1801, 4.1802, 4.1803, 4.1804)
45.2.4.14 TimeSync PHY XS receive path data delay (Registers 4.1805, 4.1806, 4.1807, 4.1808) <\/td>\n<\/tr>\n
198<\/td>\n45.2.5 DTE XS registers <\/td>\n<\/tr>\n
199<\/td>\n45.2.5.1 DTE XS control 1 register (Register 5.0) <\/td>\n<\/tr>\n
200<\/td>\n45.2.5.1.1 Reset (5.0.15)
45.2.5.1.2 Loopback (5.0.14)
45.2.5.1.3 Low power (5.0.11)
45.2.5.1.4 Clock stop enable (5.0.10) <\/td>\n<\/tr>\n
201<\/td>\n45.2.5.1.5 XAUI stop enable (5.0.9)
45.2.5.1.6 Speed selection (5.0.13, 5.0.6, 5.0.5:2)
45.2.5.2 DTE XS status 1 register (Register 5.1) <\/td>\n<\/tr>\n
202<\/td>\n45.2.5.2.1 Transmit LPI received (5.1.11)
45.2.5.2.2 Receive LPI received (5.1.10)
45.2.5.2.3 Transmit LPI indication (5.1.9)
45.2.5.2.4 Receive LPI indication (5.1.8)
45.2.5.2.5 Fault (5.1.7)
45.2.5.2.6 Clock stop capable (5.1.6)
45.2.5.2.7 DTE XS receive link status (5.1.2) <\/td>\n<\/tr>\n
203<\/td>\n45.2.5.2.8 Low-power ability (5.1.1)
45.2.5.3 DTE XS device identifier (Registers 5.2 and 5.3)
45.2.5.4 DTE XS speed ability (Register 5.4)
45.2.5.4.1 10G capable (5.4.0)
45.2.5.5 DTE XS devices in package (Registers 5.5 and 5.6)
45.2.5.6 DTE XS status 2 register (Register 5.8)
45.2.5.6.1 Device present (5.8.15:14) <\/td>\n<\/tr>\n
204<\/td>\n45.2.5.6.2 Transmit fault (5.8.11)
45.2.5.6.3 Receive fault (5.8.10)
45.2.5.7 DTE XS package identifier (Registers 5.14 and 5.15) <\/td>\n<\/tr>\n
205<\/td>\n45.2.5.8 EEE capability (Register 5.20)
45.2.5.8.1 PHY XS EEE supported (5.20.4)
45.2.5.8.2 XAUI stop capable (5.20.0)
45.2.5.9 EEE wake error counter (Register 5.22)
45.2.5.10 10G DTE XGXS lane status register (Register 5.24)
45.2.5.10.1 DTE XGXS receive lane alignment status (5.24.12) <\/td>\n<\/tr>\n
206<\/td>\n45.2.5.10.2 Pattern testing ability (5.24.11)
45.2.5.10.3 Lane 3 sync (5.24.3)
45.2.5.10.4 Lane 2 sync (5.24.2)
45.2.5.10.5 Lane 1 sync (5.24.1)
45.2.5.10.6 Lane 0 sync (5.24.0) <\/td>\n<\/tr>\n
207<\/td>\n45.2.5.11 10G DTE XGXS test control register (Register 5.25)
45.2.5.11.1 10G DTE XGXS test-pattern enable (5.25.2)
45.2.5.11.2 10G DTE XGXS test-pattern select (5.25.1:0)
45.2.5.12 TimeSync DTE XS capability (Register 5.1800) <\/td>\n<\/tr>\n
208<\/td>\n45.2.5.13 TimeSync DTE XS transmit path data delay (Registers 5.1801, 5.1802, 5.1803, 5.1804)
45.2.5.14 TimeSync DTE XS receive path data delay (Registers 5.1805, 5.1806, 5.1807, 5.1808) <\/td>\n<\/tr>\n
209<\/td>\n45.2.6 TC registers <\/td>\n<\/tr>\n
210<\/td>\n45.2.6.1 TC control register (Register 6.0)
45.2.6.1.1 Reset (6.0.15) <\/td>\n<\/tr>\n
211<\/td>\n45.2.6.1.2 Speed selection (6.0.13, 6.0.6, 6.0.5:2)
45.2.6.2 TC device identifier (Registers 6.2 and 6.3)
45.2.6.3 TC speed ability (Register 6.4) <\/td>\n<\/tr>\n
212<\/td>\n45.2.6.3.1 10PASS-TS\/2BASE-TL capable (6.4.1)
45.2.6.4 TC devices in package registers (Registers 6.5, 6.6)
45.2.6.5 TC package identifier registers (Registers 6.14, 6.15)
45.2.6.6 10P\/2B aggregation discovery control register (Register 6.16)
45.2.6.6.1 Discovery operation (6.16.1:0) <\/td>\n<\/tr>\n
213<\/td>\n45.2.6.7 10P\/2B aggregation and discovery status register (Register 6.17)
45.2.6.7.1 Link partner aggregate operation result (6.17.1) <\/td>\n<\/tr>\n
214<\/td>\n45.2.6.7.2 Discovery operation result (6.17.0)
45.2.6.8 10P\/2B aggregation discovery code (Registers 6.18, 6.19, 6.20)
45.2.6.9 10P\/2B link partner PME aggregate control register (Register 6.21) <\/td>\n<\/tr>\n
215<\/td>\n45.2.6.9.1 Link partner aggregate operation (6.21.1:0)
45.2.6.10 10P\/2B link partner PME aggregate data (Registers 6.22, 6.23) <\/td>\n<\/tr>\n
216<\/td>\n45.2.6.11 10P\/2B TC CRC error register (Register 6.24)
45.2.6.12 10P\/2B TPS-TC coding violations counter (Registers 6.25, 6.26)
45.2.6.13 10P\/2B TC indications register (Register 6.27)
45.2.6.13.1 Local TC synchronized (6.27.8)
45.2.6.13.2 Remote TC synchronized (6.27.0) <\/td>\n<\/tr>\n
217<\/td>\n45.2.6.14 TimeSync TC capability (Register 6.1800)
45.2.6.15 TimeSync TC transmit path data delay (Registers 6.1801, 6.1802, 6.1803, 6.1804) <\/td>\n<\/tr>\n
218<\/td>\n45.2.6.16 TimeSync TC receive path data delay (Registers 6.1805, 6.1806, 6.1807, 6.1808)
45.2.7 Auto-Negotiation registers <\/td>\n<\/tr>\n
219<\/td>\n45.2.7.1 AN control register (Register 7.0) <\/td>\n<\/tr>\n
220<\/td>\n45.2.7.1.1 AN reset (7.0.15)
45.2.7.1.2 Extended Next Page control (7.0.13)
45.2.7.1.3 Auto-Negotiation enable (7.0.12)
45.2.7.1.4 Restart Auto-Negotiation (7.0.9)
45.2.7.2 AN status (Register 7.1) <\/td>\n<\/tr>\n
221<\/td>\n45.2.7.2.1 Parallel detection fault (7.1.9)
45.2.7.2.2 Extended Next Page status (7.1.7)
45.2.7.2.3 Page received (7.1.6)
45.2.7.2.4 Auto-Negotiation complete (7.1.5) <\/td>\n<\/tr>\n
222<\/td>\n45.2.7.2.5 Remote fault (7.1.4)
45.2.7.2.6 Auto-Negotiation ability (7.1.3)
45.2.7.2.7 Link status (7.1.2)
45.2.7.2.8 Link partner Auto-Negotiation ability (7.1.0)
45.2.7.3 Auto-Negotiation device identifier (Registers 7.2 and 7.3)
45.2.7.4 AN devices in package (Registers 7.5 and 7.6)
45.2.7.5 AN package identifier (Registers 7.14 and 7.15) <\/td>\n<\/tr>\n
223<\/td>\n45.2.7.6 AN advertisement register (7.16, 7.17, and 7.18) <\/td>\n<\/tr>\n
224<\/td>\n45.2.7.7 AN LP Base Page ability register (7.19, 7.20, and 7.21)
45.2.7.8 AN XNP transmit register (7.22, 7.23, and 7.24) <\/td>\n<\/tr>\n
225<\/td>\n45.2.7.9 AN LP XNP ability register (7.25, 7.26, and 7.27) <\/td>\n<\/tr>\n
226<\/td>\n45.2.7.10 10GBASE-T AN control register (Register 7.32)
45.2.7.10.1 MASTER-SLAVE manual config enable (7.32.15)
45.2.7.10.2 MASTER-SLAVE config value (7.32.14) <\/td>\n<\/tr>\n
227<\/td>\n45.2.7.10.3 Port type (7.32.13)
45.2.7.10.4 10GBASE-T capability (7.32.12)
45.2.7.10.5 LD PMA training reset request (7.32.2)
45.2.7.10.6 Fast retrain ability
45.2.7.10.7 LD loop timing ability (7.32.0) <\/td>\n<\/tr>\n
228<\/td>\n45.2.7.11 10GBASE-T AN status register (Register 7.33)
45.2.7.11.1 MASTER-SLAVE configuration fault (7.33.15)
45.2.7.11.2 MASTER-SLAVE configuration resolution (7.33.14) <\/td>\n<\/tr>\n
229<\/td>\n45.2.7.11.3 Local receiver status (7.33.13)
45.2.7.11.4 Remote receiver status (7.33.12)
45.2.7.11.5 Link partner 10GBASE-T capability (7.33.11)
45.2.7.11.6 Link partner loop timing ability (7.33.10)
45.2.7.11.7 Link partner PMA training reset request (7.33.9)
45.2.7.11.8 Fast retrain ability (7.33.1)
45.2.7.12 Backplane Ethernet, BASE-R copper status (Register 7.48) <\/td>\n<\/tr>\n
230<\/td>\n45.2.7.12.1 BASE-R FEC negotiated (7.48.4)
45.2.7.12.2 Negotiated Port Type (7.48.1, 7.48.2, 7.48.3, 7.48.5, 7.48.6, 7.48.8)
45.2.7.12.3 Backplane Ethernet, BASE-R copper AN ability (7.48.0)
45.2.7.13 EEE advertisement (Register 7.60) <\/td>\n<\/tr>\n
231<\/td>\n45.2.7.13.1 10GBASE-KR EEE supported (7.60.6)
45.2.7.13.2 10GBASE-KX4 EEE supported (7.60.5) <\/td>\n<\/tr>\n
232<\/td>\n45.2.7.13.3 1000BASE-KX EEE supported (7.60.4)
45.2.7.13.4 10GBASE-T EEE supported (7.60.3)
45.2.7.13.5 1000BASE-T EEE supported (7.60.2)
45.2.7.13.6 100BASE-TX EEE supported (7.60.1)
45.2.7.14 EEE link partner ability (Register 7.61) <\/td>\n<\/tr>\n
233<\/td>\n45.2.8 Clause 22 extension registers
45.2.8.1 Clause 22 extension devices in package registers (Registers 29.5, 29.6)
45.2.8.2 FEC capability register (Register 29.7) <\/td>\n<\/tr>\n
234<\/td>\n45.2.8.2.1 FEC capable (29.7.0)
45.2.8.3 FEC control register (Register 29.8)
45.2.8.3.1 FEC enable (29.8.0)
45.2.8.4 FEC buffer head coding violation counter (Register 29.9) <\/td>\n<\/tr>\n
235<\/td>\n45.2.8.5 FEC corrected blocks counter (Register 29.10)
45.2.8.6 FEC uncorrected blocks counter (Register 29.11)
45.2.9 Vendor specific MMD 1 registers <\/td>\n<\/tr>\n
236<\/td>\n45.2.9.1 Vendor specific MMD 1 device identifier (Registers 30.2 and 30.3)
45.2.9.2 Vendor specific MMD 1 status register (Register 30.8)
45.2.9.2.1 Device present (30.8.15:14)
45.2.9.3 Vendor specific MMD 1 package identifier (Registers 30.14 and 30.15) <\/td>\n<\/tr>\n
237<\/td>\n45.2.10 Vendor specific MMD 2 registers
45.2.10.1 Vendor specific MMD 2 device identifier (Registers 31.2 and 31.3)
45.2.10.2 Vendor specific MMD 2 status register (Register 31.8) <\/td>\n<\/tr>\n
238<\/td>\n45.2.10.2.1 Device present (31.8.15:14)
45.2.10.3 Vendor specific MMD 2 package identifier (Registers 31.14 and 31.15)
45.3 Management frame structure <\/td>\n<\/tr>\n
239<\/td>\n45.3.1 IDLE (idle condition)
45.3.2 PRE (preamble)
45.3.3 ST (start of frame)
45.3.4 OP (operation code)
45.3.5 PRTAD (port address)
45.3.6 DEVAD (device address)
45.3.7 TA (turnaround) <\/td>\n<\/tr>\n
240<\/td>\n45.3.8 ADDRESS \/ DATA
45.4 Electrical interface
45.4.1 Electrical specification
45.4.2 Timing specification <\/td>\n<\/tr>\n
242<\/td>\n45.5 Protocol implementation conformance statement (PICS) proforma for Clause 45, MDIO interface
45.5.1 Introduction
45.5.2 Identification
45.5.2.1 Implementation identification
45.5.2.2 Protocol summary <\/td>\n<\/tr>\n
243<\/td>\n45.5.2.3 Major capabilities\/options
45.5.3 PICS proforma tables for the Management Data Input Output (MDIO) interface
45.5.3.1 MDIO signal functional specifications
45.5.3.2 PMA\/PMD MMD options <\/td>\n<\/tr>\n
246<\/td>\n45.5.3.3 PMA\/PMD management functions <\/td>\n<\/tr>\n
253<\/td>\n45.5.3.4 WIS options
45.5.3.5 WIS management functions <\/td>\n<\/tr>\n
257<\/td>\n45.5.3.6 PCS options <\/td>\n<\/tr>\n
258<\/td>\n45.5.3.7 PCS management functions <\/td>\n<\/tr>\n
264<\/td>\n45.5.3.8 Auto-Negotiation options
45.5.3.9 Auto-Negotiation management functions <\/td>\n<\/tr>\n
268<\/td>\n45.5.3.10 PHY XS options
45.5.3.11 PHY XS management functions <\/td>\n<\/tr>\n
270<\/td>\n45.5.3.12 DTE XS options
45.5.3.13 DTE XS management functions <\/td>\n<\/tr>\n
272<\/td>\n45.5.3.14 Vendor specific MMD 1 management functions
45.5.3.15 Vendor specific MMD 2 management functions <\/td>\n<\/tr>\n
273<\/td>\n45.5.3.16 Management frame structure <\/td>\n<\/tr>\n
274<\/td>\n45.5.3.17 TC management functions <\/td>\n<\/tr>\n
276<\/td>\n45.5.3.18 Clause 22 extension options
45.5.3.19 Clause 22 extension management functions <\/td>\n<\/tr>\n
277<\/td>\n45.5.3.20 Signal timing characteristics
45.5.3.21 Electrical characteristics <\/td>\n<\/tr>\n
279<\/td>\n46. Reconciliation Sublayer (RS) and 10 Gigabit Media Independent Interface (XGMII)
46.1 Overview <\/td>\n<\/tr>\n
280<\/td>\n46.1.1 Summary of major concepts
46.1.2 Application
46.1.3 Rate of operation <\/td>\n<\/tr>\n
281<\/td>\n46.1.4 Delay constraints
46.1.5 Allocation of functions
46.1.6 XGMII structure <\/td>\n<\/tr>\n
282<\/td>\n46.1.7 Mapping of XGMII signals to PLS service primitives
46.1.7.1 Mapping of PLS_DATA.request
46.1.7.1.1 Function
46.1.7.1.2 Semantics of the service primitive <\/td>\n<\/tr>\n
283<\/td>\n46.1.7.1.3 When generated
46.1.7.1.4 Effect of receipt
46.1.7.2 Mapping of PLS_DATA.indication
46.1.7.2.1 Function
46.1.7.2.2 Semantics of the service primitive
46.1.7.2.3 When generated
46.1.7.2.4 Effect of receipt <\/td>\n<\/tr>\n
284<\/td>\n46.1.7.3 Mapping of PLS_CARRIER.indication
46.1.7.4 Mapping of PLS_SIGNAL.indication
46.1.7.5 Mapping of PLS_DATA_VALID.indication
46.1.7.5.1 Function
46.1.7.5.2 Semantics of the service primitive
46.1.7.5.3 When generated
46.1.7.5.4 Effect of receipt
46.2 XGMII data stream <\/td>\n<\/tr>\n
285<\/td>\n46.2.1 Inter-frame
46.2.2 Preamble and start of frame delimiter <\/td>\n<\/tr>\n
286<\/td>\n46.2.3 Data
46.2.4 End of frame delimiter
46.2.5 Definition of Start of Packet and End of Packet Delimiters
46.3 XGMII functional specifications <\/td>\n<\/tr>\n
287<\/td>\n46.3.1 Transmit
46.3.1.1 TX_CLK (10 Gb\/s transmit clock)
46.3.1.2 TXC (transmit control)
46.3.1.3 TXD (transmit data) <\/td>\n<\/tr>\n
289<\/td>\n46.3.1.4 Start control character alignment <\/td>\n<\/tr>\n
290<\/td>\n46.3.1.5 Transmit direction LPI transition <\/td>\n<\/tr>\n
291<\/td>\n46.3.2 Receive
46.3.2.1 RX_CLK (receive clock)
46.3.2.2 RXC (receive control) <\/td>\n<\/tr>\n
293<\/td>\n46.3.2.3 RXD (receive data)
46.3.2.4 Receive direction LPI transition <\/td>\n<\/tr>\n
294<\/td>\n46.3.3 Error and fault handling
46.3.3.1 Response to error indications by the XGMII
46.3.3.2 Conditions for generation of transmit Error control characters
46.3.3.3 Response to received invalid frame sequences <\/td>\n<\/tr>\n
295<\/td>\n46.3.4 Link fault signaling <\/td>\n<\/tr>\n
296<\/td>\n46.3.4.1 Conventions
46.3.4.2 Variables and counters
46.3.4.3 State Diagram <\/td>\n<\/tr>\n
297<\/td>\n46.4 LPI Assertion and Detection <\/td>\n<\/tr>\n
298<\/td>\n46.4.1 LPI messages
46.4.2 Transmit LPI state diagram <\/td>\n<\/tr>\n
299<\/td>\n46.4.2.1 Variables and counters
46.4.2.2 State diagram
46.4.3 Considerations for transmit system behavior
46.4.3.1 Considerations for receive system behavior <\/td>\n<\/tr>\n
300<\/td>\n46.5 XGMII electrical characteristics <\/td>\n<\/tr>\n
303<\/td>\n46.6 Protocol implementation conformance statement (PICS) proforma for Clause 46, Reconciliation Sublayer (RS) and 10 Gigabit Media Independent Interface (XGMII)
46.6.1 Introduction
46.6.2 Identification
46.6.2.1 Implementation identification
46.6.2.2 Protocol summary <\/td>\n<\/tr>\n
304<\/td>\n46.6.2.3 Major capabilities\/options
46.6.3 PICS proforma Tables for Reconciliation Sublayer and 10 Gigabit Media Independent Interface
46.6.3.1 General
46.6.3.2 Mapping of PLS service primitives <\/td>\n<\/tr>\n
305<\/td>\n46.6.3.3 Data stream structure <\/td>\n<\/tr>\n
306<\/td>\n46.6.3.4 LPI functions
46.6.3.5 Link Interruption
46.6.3.6 XGMII signal functional specifications <\/td>\n<\/tr>\n
307<\/td>\n46.6.3.7 Link fault signaling state diagram <\/td>\n<\/tr>\n
308<\/td>\n46.6.3.8 Electrical characteristics <\/td>\n<\/tr>\n
309<\/td>\n47. XGMII Extender Sublayer (XGXS) and 10 Gigabit Attachment Unit Interface (XAUI)
47.1 Overview <\/td>\n<\/tr>\n
310<\/td>\n47.1.1 Summary of major concepts
47.1.2 Application
47.1.3 Rate of operation <\/td>\n<\/tr>\n
311<\/td>\n47.1.4 Allocation of functions
47.1.5 Global signal detect function
47.1.6 Global transmit disable function
47.2 Functional specifications
47.2.1 PCS and PMA functionality <\/td>\n<\/tr>\n
312<\/td>\n47.2.2 Delay constraints
47.3 XAUI Electrical characteristics
47.3.1 Signal levels
47.3.2 Signal paths <\/td>\n<\/tr>\n
313<\/td>\n47.3.3 Driver characteristics
47.3.3.1 Load
47.3.3.2 Amplitude and swing <\/td>\n<\/tr>\n
314<\/td>\n47.3.3.3 Transition time
47.3.3.4 Output impedance
47.3.3.5 Driver template and jitter <\/td>\n<\/tr>\n
315<\/td>\n47.3.4 Receiver characteristics
47.3.4.1 Bit error ratio
47.3.4.2 Reference input signals <\/td>\n<\/tr>\n
316<\/td>\n47.3.4.3 Input signal amplitude
47.3.4.4 AC coupling
47.3.4.5 Input impedance
47.3.4.6 Jitter tolerance <\/td>\n<\/tr>\n
317<\/td>\n47.3.4.7 EEE receiver timing
47.3.5 Interconnect characteristics
47.3.5.1 Characteristic impedance
47.3.5.2 Connector impedance <\/td>\n<\/tr>\n
318<\/td>\n47.4 Electrical measurement requirements
47.4.1 Compliance interconnect definition <\/td>\n<\/tr>\n
319<\/td>\n47.4.2 Eye template measurements <\/td>\n<\/tr>\n
320<\/td>\n47.4.3 Jitter test requirements
47.4.3.1 Transmit jitter
47.4.3.2 Jitter tolerance
47.5 Environmental specifications <\/td>\n<\/tr>\n
321<\/td>\n47.6 Protocol implementation conformance statement (PICS) proforma for Clause 47, XGMII Extender (XGMII) and 10 Gigabit Attachment Unit Interface (XAUI)
47.6.1 Introduction
47.6.2 Identification
47.6.2.1 Implementation identification
47.6.2.2 Protocol summary <\/td>\n<\/tr>\n
322<\/td>\n47.6.3 Major capabilities\/options
47.6.4 PICS Proforma tables for XGXS and XAUI
47.6.4.1 Compatibility considerations
47.6.4.2 XGXS and XAUI functions
47.6.4.3 Electrical characteristics <\/td>\n<\/tr>\n
323<\/td>\n47.6.4.4 LPI functions <\/td>\n<\/tr>\n
325<\/td>\n48. Physical Coding Sublayer (PCS) and Physical Medium Attachment (PMA) sublayer, type 10GBASE-X
48.1 Overview
48.1.1 Objectives <\/td>\n<\/tr>\n
326<\/td>\n48.1.2 Relationship of 10GBASE-X to other standards
48.1.3 Summary of 10GBASE-X sublayers
48.1.3.1 Physical Coding Sublayer (PCS) <\/td>\n<\/tr>\n
327<\/td>\n48.1.3.2 Physical Medium Attachment (PMA) sublayer
48.1.3.3 Physical Medium Dependent (PMD) sublayer
48.1.4 Rate of operation
48.1.5 Allocation of functions <\/td>\n<\/tr>\n
328<\/td>\n48.1.6 Inter-sublayer interfaces
48.1.7 Functional block diagram <\/td>\n<\/tr>\n
329<\/td>\n48.1.8 Special symbols
48.2 Physical Coding Sublayer (PCS)
48.2.1 PCS service interface (XGMII)
48.2.2 Functions within the PCS <\/td>\n<\/tr>\n
330<\/td>\n48.2.3 Use of code-groups <\/td>\n<\/tr>\n
332<\/td>\n48.2.4 Ordered_sets and special code-groups
48.2.4.1 Data (\/D\/) <\/td>\n<\/tr>\n
334<\/td>\n48.2.4.2 Idle (||I||) and Low Power Idle (||LPIDLE||) <\/td>\n<\/tr>\n
335<\/td>\n48.2.4.2.1 Sync ||K|| <\/td>\n<\/tr>\n
336<\/td>\n48.2.4.2.2 Align ||A||
48.2.4.2.3 Skip ||R|| <\/td>\n<\/tr>\n
337<\/td>\n48.2.4.3 Encapsulation
48.2.4.3.1 Start ||S||
48.2.4.3.2 Terminate ||T||
48.2.4.4 Error \/E\/
48.2.4.5 Link status <\/td>\n<\/tr>\n
338<\/td>\n48.2.4.5.1 Sequence ||Q||
48.2.5 Management function requirements <\/td>\n<\/tr>\n
339<\/td>\n48.2.6 Detailed functions and state diagrams
48.2.6.1 State variables
48.2.6.1.1 Notation conventions <\/td>\n<\/tr>\n
340<\/td>\n48.2.6.1.2 Constants <\/td>\n<\/tr>\n
341<\/td>\n48.2.6.1.3 Variables <\/td>\n<\/tr>\n
344<\/td>\n48.2.6.1.4 Functions <\/td>\n<\/tr>\n
345<\/td>\n48.2.6.1.5 Counters
48.2.6.1.6 Timers <\/td>\n<\/tr>\n
346<\/td>\n48.2.6.1.7 Messages <\/td>\n<\/tr>\n
347<\/td>\n48.2.6.2 State diagrams
48.2.6.2.1 Transmit
48.2.6.2.2 Synchronization <\/td>\n<\/tr>\n
349<\/td>\n48.2.6.2.3 Deskew
48.2.6.2.4 Receive
48.2.6.2.5 LPI state diagrams <\/td>\n<\/tr>\n
355<\/td>\n48.2.6.2.6 LPI status and management <\/td>\n<\/tr>\n
356<\/td>\n48.2.6.3 Initialization process
48.2.6.4 Link status reporting
48.2.6.4.1 Link status detection
48.2.6.4.2 Link status signaling
48.2.6.4.3 Link status messages
48.2.7 Auto-Negotiation for Backplane Ethernet
48.3 Physical Medium Attachment (PMA) sublayer <\/td>\n<\/tr>\n
357<\/td>\n48.3.1 Functions within the PMA
48.3.1.1 PMA transmit process
48.3.1.2 PMA receive process <\/td>\n<\/tr>\n
358<\/td>\n48.3.2 Service interface
48.3.2.1 PMA_UNITDATA.request
48.3.2.1.1 Semantics of the service primitive
48.3.2.1.2 When generated
48.3.2.1.3 Effect of receipt
48.3.2.2 PMA_UNITDATA.indication
48.3.2.2.1 Semantics of the service primitive
48.3.2.2.2 When generated
48.3.2.2.3 Effect of receipt <\/td>\n<\/tr>\n
359<\/td>\n48.3.3 Loopback mode
48.3.3.1 Receiver considerations
48.3.3.2 Transmitter considerations
48.3.4 Test functions
48.4 Compatibility considerations
48.5 Delay constraints <\/td>\n<\/tr>\n
360<\/td>\n48.6 Environmental specifications <\/td>\n<\/tr>\n
361<\/td>\n48.7 Protocol implementation conformance statement (PICS) proforma for Physical Coding Sublayer (PCS) and Physical Medium Attachment (PMA) sublayer, type 10GBASE-X
48.7.1 Introduction
48.7.2 Identification
48.7.2.1 Implementation identification
48.7.2.2 Protocol summary <\/td>\n<\/tr>\n
362<\/td>\n48.7.3 Major capabilities\/options
48.7.4 PICS proforma tables for the PCS and PMA sublayer, type 10GBASE-X
48.7.4.1 Compatibility considerations
48.7.4.2 PCS functions <\/td>\n<\/tr>\n
364<\/td>\n48.7.4.3 PMA Functions
48.7.4.4 Interface functions
48.7.4.5 LPI functions <\/td>\n<\/tr>\n
365<\/td>\n49. Physical Coding Sublayer (PCS) for 64B\/66B, type 10GBASE-R
49.1 Overview
49.1.1 Scope
49.1.2 Objectives
49.1.3 Relationship of 10GBASE-R to other standards <\/td>\n<\/tr>\n
366<\/td>\n49.1.4 Summary of 10GBASE-R and 10GBASE-W sublayers
49.1.4.1 Physical Coding Sublayer (PCS) <\/td>\n<\/tr>\n
367<\/td>\n49.1.4.2 WAN Interface Sublayer (WIS)
49.1.4.3 Physical Medium Attachment (PMA) sublayer
49.1.4.4 Physical Medium Dependent (PMD) sublayer
49.1.4.5 Bit ordering across 10GBASE-R and 10GBASE-W sublayers. <\/td>\n<\/tr>\n
368<\/td>\n49.1.5 Inter-sublayer interfaces <\/td>\n<\/tr>\n
369<\/td>\n49.1.6 Functional block diagram <\/td>\n<\/tr>\n
370<\/td>\n49.2 Physical Coding Sublayer (PCS)
49.2.1 PCS service interface (XGMII)
49.2.2 Functions within the PCS <\/td>\n<\/tr>\n
371<\/td>\n49.2.3 Use of blocks
49.2.4 64B\/66B transmission code
49.2.4.1 Notation conventions <\/td>\n<\/tr>\n
372<\/td>\n49.2.4.2 Transmission order
49.2.4.3 Block structure <\/td>\n<\/tr>\n
374<\/td>\n49.2.4.4 Control codes
49.2.4.5 Ordered sets <\/td>\n<\/tr>\n
375<\/td>\n49.2.4.6 Valid and invalid blocks
49.2.4.7 Idle (\/I\/) <\/td>\n<\/tr>\n
376<\/td>\n49.2.4.8 Start (\/S\/)
49.2.4.9 Terminate (\/T\/)
49.2.4.10 ordered_set (\/O\/)
49.2.4.11 Error (\/E\/) <\/td>\n<\/tr>\n
377<\/td>\n49.2.5 Transmit process
49.2.6 Scrambler <\/td>\n<\/tr>\n
378<\/td>\n49.2.7 Gearbox
49.2.8 Test-pattern generators <\/td>\n<\/tr>\n
379<\/td>\n49.2.9 Block synchronization
49.2.10 Descrambler
49.2.11 Receive process <\/td>\n<\/tr>\n
380<\/td>\n49.2.12 Test-pattern checker <\/td>\n<\/tr>\n
381<\/td>\n49.2.13 Detailed functions and state diagrams
49.2.13.1 State diagram conventions
49.2.13.2 State variables
49.2.13.2.1 Constants
49.2.13.2.2 Variables <\/td>\n<\/tr>\n
383<\/td>\n49.2.13.2.3 Functions <\/td>\n<\/tr>\n
384<\/td>\n49.2.13.2.4 Counters <\/td>\n<\/tr>\n
385<\/td>\n49.2.13.2.5 Timers <\/td>\n<\/tr>\n
386<\/td>\n49.2.13.3 State diagrams
49.2.13.3.1 LPI state diagrams <\/td>\n<\/tr>\n
389<\/td>\n49.2.14 PCS Management
49.2.14.1 Status <\/td>\n<\/tr>\n
390<\/td>\n49.2.14.2 Counters
49.2.14.3 Test mode control
49.2.14.4 Loopback
49.2.15 Delay constraints <\/td>\n<\/tr>\n
391<\/td>\n49.2.16 Auto-Negotiation for Backplane Ethernet <\/td>\n<\/tr>\n
395<\/td>\n49.3 Protocol implementation conformance statement (PICS) proforma for Clause 49, Physical Coding Sublayer (PCS) type 10GBASE-R
49.3.1 Introduction
49.3.2 Identification
49.3.2.1 Implementation identification
49.3.2.2 Protocol summary <\/td>\n<\/tr>\n
396<\/td>\n49.3.3 Major capabilities\/options
49.3.4 PICS Proforma Tables for PCS, type 10GBASE-R
49.3.4.1 Coding rules <\/td>\n<\/tr>\n
397<\/td>\n49.3.4.2 Scrambler and Descrambler
49.3.5 Test-pattern modes <\/td>\n<\/tr>\n
398<\/td>\n49.3.5.1 Bit order
49.3.6 Management
49.3.6.1 State diagrams <\/td>\n<\/tr>\n
399<\/td>\n49.3.6.2 WIS
49.3.6.3 Loopback
49.3.6.4 Delay Constraints
49.3.6.5 Auto-Negotiation for Backplane Ethernet functions <\/td>\n<\/tr>\n
400<\/td>\n49.3.6.6 LPI functions <\/td>\n<\/tr>\n
401<\/td>\n50. WAN Interface Sublayer (WIS), type 10GBASE-W
50.1 Overview
50.1.1 Scope <\/td>\n<\/tr>\n
402<\/td>\n50.1.2 Objectives <\/td>\n<\/tr>\n
403<\/td>\n50.1.3 Relationship to other sublayers
50.1.4 Summary of functions <\/td>\n<\/tr>\n
404<\/td>\n50.1.5 Sublayer interfaces
50.1.6 Functional block diagram
50.1.7 Notational conventions <\/td>\n<\/tr>\n
405<\/td>\n50.2 WIS Service Interface
50.2.1 WIS_UNITDATA.request
50.2.1.1 Semantics of the service primitive
50.2.1.2 When generated <\/td>\n<\/tr>\n
406<\/td>\n50.2.1.3 Effect of receipt
50.2.2 WIS_UNITDATA.indication
50.2.2.1 Semantics of the service primitive
50.2.2.2 When generated
50.2.2.3 Effect of receipt
50.2.3 WIS_SIGNAL.request
50.2.3.1 Semantics of the service primitive <\/td>\n<\/tr>\n
407<\/td>\n50.2.3.2 When generated
50.2.3.3 Effect of receipt
50.2.4 WIS_SIGNAL.indication
50.2.4.1 Semantics of the service primitive
50.2.4.2 When generated
50.2.4.3 Effect of receipt
50.3 Functions within the WIS <\/td>\n<\/tr>\n
409<\/td>\n50.3.1 Payload mapping and data-unit delineation <\/td>\n<\/tr>\n
410<\/td>\n50.3.1.1 Transmit payload mapping <\/td>\n<\/tr>\n
411<\/td>\n50.3.1.2 Receive payload mapping
50.3.2 WIS frame generation <\/td>\n<\/tr>\n
412<\/td>\n50.3.2.1 Transmit Path Overhead insertion <\/td>\n<\/tr>\n
413<\/td>\n50.3.2.2 Transmit Line Overhead insertion <\/td>\n<\/tr>\n
414<\/td>\n50.3.2.3 Transmit Section Overhead insertion <\/td>\n<\/tr>\n
415<\/td>\n50.3.2.4 Receive Path, Line, and Section Overhead extraction <\/td>\n<\/tr>\n
416<\/td>\n50.3.2.5 Fault processing <\/td>\n<\/tr>\n
417<\/td>\n50.3.3 Scrambling <\/td>\n<\/tr>\n
418<\/td>\n50.3.3.1 Scrambler polynomial
50.3.3.2 Scrambler bit ordering
50.3.4 Octet and frame delineation
50.3.5 Error propagation <\/td>\n<\/tr>\n
419<\/td>\n50.3.5.1 Propagated errors
50.3.5.2 Error propagation timing
50.3.5.3 Loss of Code-group Delineation
50.3.6 Mapping between WIS and PMA <\/td>\n<\/tr>\n
420<\/td>\n50.3.7 WIS data delay constraints <\/td>\n<\/tr>\n
421<\/td>\n50.3.8 WIS test-pattern generator and checker
50.3.8.1 Square wave test pattern
50.3.8.2 PRBS31 test pattern <\/td>\n<\/tr>\n
422<\/td>\n50.3.8.3 Mixed-frequency test pattern <\/td>\n<\/tr>\n
423<\/td>\n50.3.8.3.1 Test Signal Structure (TSS) <\/td>\n<\/tr>\n
424<\/td>\n50.3.8.3.2 Continuous Identical Digits
50.3.9 Loopback
50.3.10 Link status
50.3.11 Management interface <\/td>\n<\/tr>\n
425<\/td>\n50.3.11.1 Management registers
50.3.11.2 WIS managed object class
50.3.11.3 Management support objects <\/td>\n<\/tr>\n
426<\/td>\n50.4 Synchronization state diagram
50.4.1 State diagram variables
50.4.1.1 Constants <\/td>\n<\/tr>\n
427<\/td>\n50.4.1.2 Variables
50.4.1.3 Functions <\/td>\n<\/tr>\n
428<\/td>\n50.4.1.4 Counters
50.4.2 State diagram <\/td>\n<\/tr>\n
430<\/td>\n50.4.3 Parameter values
50.5 Environmental specifications <\/td>\n<\/tr>\n
432<\/td>\n50.6 Protocol implementation conformance statement (PICS) proforma for Clause 50, WAN Interface Sublayer (WIS), type 10GBASE-W
50.6.1 Introduction
50.6.2 Identification
50.6.2.1 Implementation identification
50.6.2.2 Protocol summary <\/td>\n<\/tr>\n
433<\/td>\n50.6.3 Major capabilities\/options
50.6.4 PICS proforma tables for the WAN Interface Sublayer (WIS), type 10GBASE-W
50.6.4.1 Compatibility considerations
50.6.4.2 WIS transmit functions <\/td>\n<\/tr>\n
434<\/td>\n50.6.4.3 WIS receive functions <\/td>\n<\/tr>\n
435<\/td>\n50.6.4.4 State diagrams <\/td>\n<\/tr>\n
436<\/td>\n50.6.4.5 Error notification
50.6.4.6 Management registers and functions <\/td>\n<\/tr>\n
437<\/td>\n50.6.4.7 WIS test-pattern generator and checker <\/td>\n<\/tr>\n
439<\/td>\n51. Physical Medium Attachment (PMA) sublayer, type Serial
51.1 Overview
51.1.1 Scope
51.1.2 Summary of functions <\/td>\n<\/tr>\n
440<\/td>\n51.2 PMA Service Interface
51.2.1 PMA_UNITDATA.request
51.2.1.1 Semantics of the service primitive
51.2.1.2 When generated <\/td>\n<\/tr>\n
441<\/td>\n51.2.1.3 Effect of receipt
51.2.2 PMA_UNITDATA.indication
51.2.2.1 Semantics of the service primitive
51.2.2.2 When generated
51.2.2.3 Effect of receipt
51.2.3 PMA_SIGNAL.indication
51.2.3.1 Semantics of the service primitive
51.2.3.2 When generated
51.2.3.3 Effect of receipt <\/td>\n<\/tr>\n
442<\/td>\n51.2.4 PMA_RXMODE.request
51.2.4.1 Semantics of the service primitive
51.2.4.2 When generated
51.2.4.3 Effect of receipt
51.2.5 PMA_TXMODE.request
51.2.5.1 Semantics of the service primitive
51.2.5.2 When generated
51.2.5.3 Effect of receipt
51.2.6 PMA_ENERGY.indication
51.2.6.1 Semantics of the service primitive <\/td>\n<\/tr>\n
443<\/td>\n51.2.6.2 When generated
51.2.6.3 Effect of receipt
51.3 Functions within the PMA
51.3.1 PMA transmit function
51.3.2 PMA receive function
51.3.3 Delay Constraints <\/td>\n<\/tr>\n
444<\/td>\n51.4 Sixteen-Bit Interface (XSBI) <\/td>\n<\/tr>\n
445<\/td>\n51.4.1 Required signals <\/td>\n<\/tr>\n
447<\/td>\n51.4.2 Optional Signals <\/td>\n<\/tr>\n
448<\/td>\n51.5 General electrical characteristics of the XSBI
51.5.1 DC characteristics
51.5.2 Valid signal levels <\/td>\n<\/tr>\n
449<\/td>\n51.5.3 Rise and fall time definition
51.5.4 Output load
51.6 XSBI transmit interface electrical characteristics
51.6.1 XSBI transmit interface timing <\/td>\n<\/tr>\n
450<\/td>\n51.6.1.1 PMA client output timing <\/td>\n<\/tr>\n
451<\/td>\n51.6.1.2 PMA input timing
51.6.2 XSBI PMA_TX_CLK and PMA_TXCLK_SRC Specification <\/td>\n<\/tr>\n
452<\/td>\n51.7 XSBI receive interface electrical characteristics
51.7.1 XSBI receive interface timing <\/td>\n<\/tr>\n
453<\/td>\n51.7.1.1 PMA output timing <\/td>\n<\/tr>\n
454<\/td>\n51.7.1.2 PMA client input timing
51.7.2 XSBI PMA_RX_CLK specification
51.8 PMA loopback mode (optional) <\/td>\n<\/tr>\n
455<\/td>\n51.9 Environmental specifications <\/td>\n<\/tr>\n
456<\/td>\n51.10 Protocol implementation conformance statement (PICS) proforma for Clause 51, Physical Medium Attachment (PMA) sublayer, type Serial
51.10.1 Introduction
51.10.2 Identification
51.10.2.1 Implementation identification
51.10.2.2 Protocol summary <\/td>\n<\/tr>\n
457<\/td>\n51.10.3 Major capabilities\/options
51.10.4 PICS proforma tables for the PMA Interface Sublayer, type Serial
51.10.4.1 Compatibility considerations
51.10.4.2 PMA transmit functions <\/td>\n<\/tr>\n
458<\/td>\n51.10.4.3 PMA receive functions
51.10.4.4 PMA delay constraints <\/td>\n<\/tr>\n
459<\/td>\n52. Physical Medium Dependent (PMD) sublayer and baseband medium, type 10GBASE-S (short wavelength serial), 10GBASE-L (long wavelength serial), and 10GBASE-E (extra long wavelength serial)
52.1 Overview <\/td>\n<\/tr>\n
460<\/td>\n52.1.1 Physical Medium Dependent (PMD) sublayer service interface
52.1.1.1 PMD_UNITDATA.request <\/td>\n<\/tr>\n
461<\/td>\n52.1.1.1.1 Semantics of the service primitive
52.1.1.1.2 When generated
52.1.1.1.3 Effect of receipt
52.1.1.2 PMD_UNITDATA.indication
52.1.1.2.1 Semantics of the service primitive
52.1.1.2.2 When generated
52.1.1.2.3 Effect of receipt
52.1.1.3 PMD_SIGNAL.indication
52.1.1.3.1 Semantics of the service primitive <\/td>\n<\/tr>\n
462<\/td>\n52.1.1.3.2 When generated
52.1.1.3.3 Effect of receipt
52.2 Delay constraints
52.3 PMD MDIO function mapping <\/td>\n<\/tr>\n
463<\/td>\n52.4 PMD functional specifications
52.4.1 PMD block diagram
52.4.2 PMD Transmit function
52.4.3 PMD Receive function
52.4.4 PMD Signal Detect function <\/td>\n<\/tr>\n
464<\/td>\n52.4.5 PMD_reset function
52.4.6 PMD_fault function
52.4.7 PMD_global_transmit_disable function <\/td>\n<\/tr>\n
465<\/td>\n52.4.8 PMD_transmit_fault function
52.4.9 PMD_receive_fault function
52.5 PMD to MDI optical specifications for 10GBASE-S <\/td>\n<\/tr>\n
466<\/td>\n52.5.1 10GBASE-S transmitter optical specifications <\/td>\n<\/tr>\n
468<\/td>\n52.5.2 10GBASE-S receive optical specifications
52.5.3 10GBASE-S link power budgets (informative)
52.6 PMD to MDI optical specifications for 10GBASE-L <\/td>\n<\/tr>\n
469<\/td>\n52.6.1 10GBASE-L transmitter optical specifications <\/td>\n<\/tr>\n
471<\/td>\n52.6.2 10GBASE-L receive optical specifications
52.6.3 10GBASE-L link power budgets (informative) <\/td>\n<\/tr>\n
472<\/td>\n52.7 PMD to MDI optical specifications for 10GBASE-E <\/td>\n<\/tr>\n
473<\/td>\n52.7.1 10GBASE-E transmitter optical specifications <\/td>\n<\/tr>\n
474<\/td>\n52.7.2 10GBASE-E receive optical specifications
52.7.3 10GBASE-E link power budgets (informative)
52.8 Jitter specifications for 10GBASE-R and 10GBASE-W <\/td>\n<\/tr>\n
475<\/td>\n52.8.1 Sinusoidal jitter for receiver conformance test <\/td>\n<\/tr>\n
476<\/td>\n52.9 Optical measurement requirements
52.9.1 Test patterns
52.9.1.1 Test-pattern definition <\/td>\n<\/tr>\n
478<\/td>\n52.9.1.2 Square wave pattern definition
52.9.2 Center wavelength and spectral width measurements
52.9.3 Average optical power measurements
52.9.4 Extinction ratio measurements
52.9.5 Optical modulation amplitude (OMA) test procedure <\/td>\n<\/tr>\n
479<\/td>\n52.9.6 Relative intensity noise optical modulation amplitude (RINxOMA) measuring procedure
52.9.6.1 General test description
52.9.6.2 Component descriptions <\/td>\n<\/tr>\n
480<\/td>\n52.9.6.3 Test Procedure <\/td>\n<\/tr>\n
481<\/td>\n52.9.7 Transmitter optical waveform <\/td>\n<\/tr>\n
482<\/td>\n52.9.8 Receiver sensitivity measurements <\/td>\n<\/tr>\n
483<\/td>\n52.9.9 Stressed receiver conformance test
52.9.9.1 Stressed receiver conformance test block diagram <\/td>\n<\/tr>\n
485<\/td>\n52.9.9.2 Parameter definitions <\/td>\n<\/tr>\n
486<\/td>\n52.9.9.3 Stressed receiver conformance test signal characteristics and calibration <\/td>\n<\/tr>\n
487<\/td>\n52.9.9.4 Stressed receiver conformance test procedure <\/td>\n<\/tr>\n
488<\/td>\n52.9.10 Transmitter and dispersion penalty measurement
52.9.10.1 Reference transmitter requirements
52.9.10.2 Channel requirements <\/td>\n<\/tr>\n
489<\/td>\n52.9.10.3 Reference receiver requirements
52.9.10.4 Test procedure <\/td>\n<\/tr>\n
490<\/td>\n52.9.11 Measurement of the receiver 3 dB electrical upper cutoff frequency <\/td>\n<\/tr>\n
491<\/td>\n52.10 Environmental specifications
52.10.1 General safety
52.10.2 Laser safety
52.10.3 Installation
52.11 Environment
52.11.1 Electromagnetic emission <\/td>\n<\/tr>\n
492<\/td>\n52.11.2 Temperature, humidity, and handling
52.12 PMD labeling requirements
52.13 Fiber optic cabling model <\/td>\n<\/tr>\n
493<\/td>\n52.14 Characteristics of the fiber optic cabling (channel)
52.14.1 Optical fiber and cable
52.14.2 Optical fiber connection
52.14.2.1 Connection insertion loss <\/td>\n<\/tr>\n
494<\/td>\n52.14.2.2 Maximum discrete reflectance
52.14.3 10GBASE-E attenuator management <\/td>\n<\/tr>\n
495<\/td>\n52.14.4 Medium Dependent Interface (MDI) requirements <\/td>\n<\/tr>\n
496<\/td>\n52.15 Protocol implementation conformance statement (PICS) proforma for Clause 52, Physical Medium Dependent (PMD) sublayer and baseband medium, type 10GBASE-S (short wavelength serial), 10GBASE-L (long wavelength serial), and 10GBASE-E (extra long w…
52.15.1 Introduction
52.15.2 Identification
52.15.2.1 Implementation identification
52.15.2.2 Protocol summary <\/td>\n<\/tr>\n
497<\/td>\n52.15.2.3 Major capabilities\/options <\/td>\n<\/tr>\n
498<\/td>\n52.15.3 PICS proforma tables for Physical Medium Dependent (PMD) sublayer and baseband medium, types 10GBASE-R and 10GBASE-W
52.15.3.1 PMD functional specifications
52.15.3.2 Management functions <\/td>\n<\/tr>\n
499<\/td>\n52.15.3.3 PMD to MDI optical specifications for 10GBASE-SR
52.15.3.4 PMD to MDI optical specifications for 10GBASE-SW
52.15.3.5 PMD to MDI optical specifications for 10GBASE-LR <\/td>\n<\/tr>\n
500<\/td>\n52.15.3.6 PMD to MDI optical specifications for 10GBASE-LW
52.15.3.7 PMD to MDI optical specifications for 10GBASE-ER
52.15.3.8 PMD to MDI optical specifications for 10GBASE-EW <\/td>\n<\/tr>\n
501<\/td>\n52.15.3.9 Optical measurement requirements
52.15.3.10 Characteristics of the fiber optic cabling and MDI <\/td>\n<\/tr>\n
502<\/td>\n52.15.3.11 Environmental specifications
52.15.3.12 Environment <\/td>\n<\/tr>\n
503<\/td>\n53. Physical Medium Dependent (PMD) sublayer and baseband medium, type 10GBASE-LX4
53.1 Overview
53.1.1 Physical Medium Dependent (PMD) service interface
53.1.2 PMD_UNITDATA.request <\/td>\n<\/tr>\n
504<\/td>\n53.1.2.1 Semantics of the service primitive
53.1.2.2 When generated
53.1.2.3 Effect of Receipt
53.1.3 PMD_UNITDATA.indication
53.1.3.1 Semantics of the service primitive <\/td>\n<\/tr>\n
505<\/td>\n53.1.3.2 When generated
53.1.3.3 Effect of receipt
53.1.4 PMD_SIGNAL.indication
53.1.4.1 Semantics of the service primitive
53.1.4.2 When generated
53.1.4.3 Effect of receipt
53.2 Delay constraints
53.3 PMD MDIO function mapping <\/td>\n<\/tr>\n
506<\/td>\n53.4 PMD functional specifications
53.4.1 PMD block diagram <\/td>\n<\/tr>\n
507<\/td>\n53.4.2 PMD transmit function <\/td>\n<\/tr>\n
508<\/td>\n53.4.3 PMD receive function
53.4.4 Global PMD signal detect function
53.4.5 PMD lane by lane signal detect function <\/td>\n<\/tr>\n
509<\/td>\n53.4.6 PMD reset function
53.4.7 Global PMD transmit disable function
53.4.8 PMD lane by lane transmit disable function
53.4.9 PMD fault function
53.4.10 PMD transmit fault function (optional)
53.4.11 PMD receive fault function (optional)
53.5 Wavelength-division multiplexed-lane assignments
53.6 Operating ranges for 10GBASE-LX4 PMD <\/td>\n<\/tr>\n
511<\/td>\n53.7 PMD to MDI optical specifications for 10GBASE-LX4
53.7.1 Transmitter optical specifications <\/td>\n<\/tr>\n
512<\/td>\n53.7.2 Receive optical specifications
53.7.3 Worst case 10GBASE-LX4 link power budget and penalties (informative)
53.8 Jitter specifications for each lane of the 10GBASE-LX4 PMD
53.8.1 Transmit jitter specification <\/td>\n<\/tr>\n
514<\/td>\n53.8.1.1 Channel requirements for transmit jitter testing
53.8.1.2 Test pattern requirements for transmit jitter testing
53.8.2 Receive jitter tolerance specification
53.8.2.1 Input jitter for receiver jitter test <\/td>\n<\/tr>\n
515<\/td>\n53.8.2.2 Added sinusoidal jitter for receiver jitter test <\/td>\n<\/tr>\n
516<\/td>\n53.9 Optical measurement requirements
53.9.1 Wavelength range measurements <\/td>\n<\/tr>\n
517<\/td>\n53.9.2 Optical power measurements
53.9.3 Source spectral window measurements
53.9.4 Extinction ratio measurements
53.9.5 Optical Modulation Amplitude (OMA) measurements
53.9.6 Relative Intensity Noise [RIN12(OMA)]
53.9.7 Transmitter optical waveform (transmit eye) <\/td>\n<\/tr>\n
519<\/td>\n53.9.8 Transmit rise\/fall characteristics
53.9.9 Receive sensitivity measurements
53.9.10 Transmitter jitter conformance (per lane)
53.9.10.1 Block diagram and general description of test set up <\/td>\n<\/tr>\n
520<\/td>\n53.9.10.2 Channel requirements for transmit jitter testing <\/td>\n<\/tr>\n
521<\/td>\n53.9.10.3 Transmit jitter test procedure
53.9.11 Receive sensitivity measurements
53.9.12 Stressed receiver conformance test
53.9.12.1 Block diagram of stressed receiver tolerance test set up <\/td>\n<\/tr>\n
522<\/td>\n53.9.12.2 Stressed receiver conformance test procedure
53.9.12.3 Characterization of receiver input signal <\/td>\n<\/tr>\n
523<\/td>\n53.9.12.4 Jitter tolerance test procedure
53.9.13 Measurement of the receiver 3 dB electrical upper cutoff frequency <\/td>\n<\/tr>\n
524<\/td>\n53.9.14 Conformance test signal at TP3 for receiver testing <\/td>\n<\/tr>\n
526<\/td>\n53.9.15 Receiver test suite for WDM conformance testing <\/td>\n<\/tr>\n
528<\/td>\n53.10 Environmental specifications
53.10.1 General safety
53.10.2 Laser safety <\/td>\n<\/tr>\n
529<\/td>\n53.10.3 Installation
53.11 Environment
53.11.1 Electromagnetic emission
53.11.2 Temperature, humidity, and handling
53.12 PMD labeling requirements <\/td>\n<\/tr>\n
530<\/td>\n53.13 Fiber optic cabling model
53.14 Characteristics of the fiber optic cabling (channel)
53.14.1 Optical fiber and cable <\/td>\n<\/tr>\n
531<\/td>\n53.14.2 Optical fiber connection
53.14.2.1 Connection insertion loss <\/td>\n<\/tr>\n
532<\/td>\n53.14.2.2 Connection return loss
53.14.3 Medium Dependent Interface (MDI) <\/td>\n<\/tr>\n
533<\/td>\n53.15 Protocol implementation conformance statement (PICS) proforma for Clause 53, Physical Medium Dependent (PMD) sublayer and baseband medium, type 10GBASE-LX4
53.15.1 Introduction
53.15.2 Identification
53.15.2.1 Implementation identification
53.15.2.2 Protocol summary <\/td>\n<\/tr>\n
534<\/td>\n53.15.3 Major capabilities\/options <\/td>\n<\/tr>\n
535<\/td>\n53.15.4 PICS proforma tables for 10GBASE-LX4 and baseband medium
53.15.4.1 PMD Functional specifications <\/td>\n<\/tr>\n
536<\/td>\n53.15.4.2 PMD to MDI optical specifications for 10GBASE-LX4
53.15.4.3 Management functions <\/td>\n<\/tr>\n
537<\/td>\n53.15.4.4 Jitter specifications <\/td>\n<\/tr>\n
538<\/td>\n53.15.4.5 Optical measurement requirements <\/td>\n<\/tr>\n
541<\/td>\n53.15.4.6 Characteristics of the fiber optic cabling <\/td>\n<\/tr>\n
543<\/td>\n54. Physical Medium Dependent (PMD) sublayer and baseband medium, type 10GBASE-CX4
54.1 Overview <\/td>\n<\/tr>\n
544<\/td>\n54.2 Physical Medium Dependent (PMD) service interface
54.3 Delay constraints
54.4 PMD MDIO function mapping
54.5 PMD functional specifications
54.5.1 Link block diagram <\/td>\n<\/tr>\n
545<\/td>\n54.5.2 PMD Transmit function
54.5.3 PMD Receive function
54.5.4 Global PMD signal detect function <\/td>\n<\/tr>\n
546<\/td>\n54.5.5 PMD lane-by-lane signal detect function
54.5.6 Global PMD transmit disable function
54.5.7 PMD lane-by-lane transmit disable function <\/td>\n<\/tr>\n
547<\/td>\n54.5.8 Loopback mode
54.5.9 PMD fault function
54.5.10 PMD transmit fault function
54.5.11 PMD receive fault function
54.6 MDI Electrical specifications for 10GBASE-CX4
54.6.1 Signal levels
54.6.2 Signal paths <\/td>\n<\/tr>\n
548<\/td>\n54.6.3 Transmitter characteristics <\/td>\n<\/tr>\n
549<\/td>\n54.6.3.1 Test fixtures
54.6.3.2 Test-fixture impedance
54.6.3.3 Signaling speed range <\/td>\n<\/tr>\n
550<\/td>\n54.6.3.4 Output amplitude <\/td>\n<\/tr>\n
551<\/td>\n54.6.3.5 Output return loss <\/td>\n<\/tr>\n
552<\/td>\n54.6.3.6 Differential output template <\/td>\n<\/tr>\n
553<\/td>\n54.6.3.7 Transition time
54.6.3.8 Transmit jitter
54.6.3.9 Transmit jitter test requirements <\/td>\n<\/tr>\n
554<\/td>\n54.6.4 Receiver characteristics
54.6.4.1 Bit error ratio
54.6.4.2 Signaling speed range
54.6.4.3 AC-coupling
54.6.4.4 Input signal amplitude <\/td>\n<\/tr>\n
555<\/td>\n54.6.4.5 Input return loss
54.7 Cable assembly characteristics <\/td>\n<\/tr>\n
556<\/td>\n54.7.1 Characteristic impedance and reference impedance
54.7.2 Cable assembly insertion loss <\/td>\n<\/tr>\n
557<\/td>\n54.7.3 Cable assembly return loss
54.7.4 Near-End Crosstalk (NEXT)
54.7.4.1 Differential Near-End Crosstalk <\/td>\n<\/tr>\n
558<\/td>\n54.7.4.2 Multiple Disturber Near-End Crosstalk (MDNEXT) <\/td>\n<\/tr>\n
559<\/td>\n54.7.5 Far-End Crosstalk (FEXT)
54.7.5.1 Equal Level Far-End Crosstalk (ELFEXT) loss
54.7.5.2 Multiple Disturber Equal Level Far-End Crosstalk (MDELFEXT) loss <\/td>\n<\/tr>\n
560<\/td>\n54.7.6 Shielding
54.7.7 Crossover function <\/td>\n<\/tr>\n
561<\/td>\n54.8 MDI specification
54.8.1 MDI connectors
54.8.2 Connector pin assignments <\/td>\n<\/tr>\n
562<\/td>\n54.9 Environmental specifications <\/td>\n<\/tr>\n
563<\/td>\n54.10 Protocol implementation conformance statement (PICS) proforma for Clause 54, Physical Medium Dependent (PMD) sublayer and baseband medium, type 10GBASE-CX4
54.10.1 Introduction
54.10.2 Identification
54.10.2.1 Implementation identification
54.10.2.2 Protocol summary <\/td>\n<\/tr>\n
564<\/td>\n54.10.3 PICS proforma tables for 10GBASE-CX4 and baseband medium
54.10.4 Major capabilities\/options <\/td>\n<\/tr>\n
565<\/td>\n54.10.4.1 PMD Functional specifications <\/td>\n<\/tr>\n
566<\/td>\n54.10.4.2 Management functions <\/td>\n<\/tr>\n
567<\/td>\n54.10.4.3 Transmitter specifications <\/td>\n<\/tr>\n
568<\/td>\n54.10.4.4 Receiver specifications
54.10.4.5 Cable assembly specifications <\/td>\n<\/tr>\n
569<\/td>\n54.10.4.6 MDI connector specifications <\/td>\n<\/tr>\n
571<\/td>\n55. Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA) sublayer and baseband medium, type 10GBASE-T
55.1 Overview
55.1.1 Objectives <\/td>\n<\/tr>\n
572<\/td>\n55.1.2 Relationship of 10GBASE-T to other standards
55.1.3 Operation of 10GBASE-T <\/td>\n<\/tr>\n
576<\/td>\n55.1.3.1 Physical Coding Sublayer (PCS)
55.1.3.2 Physical Medium Attachment (PMA) sublayer <\/td>\n<\/tr>\n
577<\/td>\n55.1.3.3 EEE capability <\/td>\n<\/tr>\n
578<\/td>\n55.1.4 Signaling
55.1.5 Interfaces <\/td>\n<\/tr>\n
579<\/td>\n55.1.6 Conventions in this clause
55.2 10GBASE-T service primitives and interfaces
55.2.1 Technology Dependent Interface
55.2.1.1 PMA_LINK.request
55.2.1.1.1 Semantics of the primitive <\/td>\n<\/tr>\n
580<\/td>\n55.2.1.1.2 When generated
55.2.1.1.3 Effect of receipt
55.2.1.2 PMA_LINK.indication
55.2.1.2.1 Semantics of the primitive
55.2.1.2.2 When generated
55.2.1.2.3 Effect of receipt
55.2.2 PMA service interface <\/td>\n<\/tr>\n
582<\/td>\n55.2.2.1 PMA_TXMODE.indication
55.2.2.1.1 Semantics of the primitive <\/td>\n<\/tr>\n
583<\/td>\n55.2.2.1.2 When generated
55.2.2.1.3 Effect of receipt
55.2.2.2 PMA_CONFIG.indication
55.2.2.2.1 Semantics of the primitive
55.2.2.2.2 When generated
55.2.2.2.3 Effect of receipt
55.2.2.3 PMA_UNITDATA.request <\/td>\n<\/tr>\n
584<\/td>\n55.2.2.3.1 Semantics of the primitive
55.2.2.3.2 When generated
55.2.2.3.3 Effect of receipt
55.2.2.4 PMA_UNITDATA.indication
55.2.2.4.1 Semantics of the primitive <\/td>\n<\/tr>\n
585<\/td>\n55.2.2.4.2 When generated
55.2.2.4.3 Effect of receipt
55.2.2.5 PMA_SCRSTATUS.request
55.2.2.5.1 Semantics of the primitive
55.2.2.5.2 When generated
55.2.2.5.3 Effect of receipt
55.2.2.6 PMA_PCSSTATUS.request
55.2.2.6.1 Semantics of the primitive
55.2.2.6.2 When generated <\/td>\n<\/tr>\n
586<\/td>\n55.2.2.6.3 Effect of receipt
55.2.2.7 PMA_RXSTATUS.indication
55.2.2.7.1 Semantics of the primitive
55.2.2.7.2 When generated
55.2.2.7.3 Effect of receipt
55.2.2.8 PMA_REMRXSTATUS.request
55.2.2.8.1 Semantics of the primitive
55.2.2.8.2 When generated <\/td>\n<\/tr>\n
587<\/td>\n55.2.2.8.3 Effect of receipt
55.2.2.9 PMA_ALERTDETECT.indication
55.2.2.9.1 Semantics of the primitive
55.2.2.9.2 When generated
55.2.2.9.3 Effect of receipt
55.2.2.10 PCS_RX_LPI_STATUS.request
55.2.2.10.1 Semantics of the primitive
55.2.2.10.2 When generated
55.2.2.10.3 Effect of receipt <\/td>\n<\/tr>\n
588<\/td>\n55.2.2.11 PMA_PCSDATAMODE.indication
55.2.2.11.1 Semantics of the primitive
55.2.2.11.2 When generated
55.2.2.11.3 Effect of receipt
55.2.2.12 PMA_FR_ACTIVE.indication
55.2.2.12.1 Semantics of the primitive
55.2.2.12.2 When generated
55.2.2.12.3 Effect of receipt
55.3 Physical Coding Sublayer (PCS)
55.3.1 PCS service interface (XGMII)
55.3.2 PCS functions <\/td>\n<\/tr>\n
589<\/td>\n55.3.2.1 PCS Reset function <\/td>\n<\/tr>\n
590<\/td>\n55.3.2.2 PCS Transmit function <\/td>\n<\/tr>\n
591<\/td>\n55.3.2.2.1 Use of blocks
55.3.2.2.2 65B-LDPC transmission code
55.3.2.2.3 Notation conventions
55.3.2.2.4 Transmission order
55.3.2.2.5 Block structure <\/td>\n<\/tr>\n
595<\/td>\n55.3.2.2.6 Control codes
55.3.2.2.7 Ordered sets <\/td>\n<\/tr>\n
596<\/td>\n55.3.2.2.8 Valid and invalid blocks
55.3.2.2.9 Idle (\/I\/) <\/td>\n<\/tr>\n
597<\/td>\n55.3.2.2.10 LPI (\/LI\/) <\/td>\n<\/tr>\n
598<\/td>\n55.3.2.2.11 Start (\/S\/)
55.3.2.2.12 Terminate (\/T\/)
55.3.2.2.13 ordered_set (\/O\/)
55.3.2.2.14 Error (\/E\/)
55.3.2.2.15 Transmit process <\/td>\n<\/tr>\n
599<\/td>\n55.3.2.2.16 PCS scrambler. <\/td>\n<\/tr>\n
600<\/td>\n55.3.2.2.17 CRC8
55.3.2.2.18 LDPC encoder
55.3.2.2.19 DSQ128 bit mapping <\/td>\n<\/tr>\n
601<\/td>\n55.3.2.2.20 DSQ128 to 4D-PAM16 <\/td>\n<\/tr>\n
602<\/td>\n55.3.2.2.21 65B-LDPC framer
55.3.2.2.22 EEE capability <\/td>\n<\/tr>\n
603<\/td>\n55.3.2.3 PCS Receive function <\/td>\n<\/tr>\n
604<\/td>\n55.3.2.3.1 Frame and block synchronization
55.3.2.3.2 PCS descrambler
55.3.2.3.3 CRC8 receive function
55.3.3 Test-pattern generators <\/td>\n<\/tr>\n
605<\/td>\n55.3.4 PMA training side-stream scrambler polynomials <\/td>\n<\/tr>\n
606<\/td>\n55.3.4.1 Generation of bits San, Sbn, Scn, Sdn
55.3.4.2 Generation of 4D symbols TAn, TBn, TCn, TDn <\/td>\n<\/tr>\n
607<\/td>\n55.3.4.3 PMA training mode descrambler polynomials
55.3.5 LPI signaling <\/td>\n<\/tr>\n
608<\/td>\n55.3.5.1 LPI Synchronization <\/td>\n<\/tr>\n
609<\/td>\n55.3.5.2 Quiet period signaling
55.3.5.3 Refresh period signaling <\/td>\n<\/tr>\n
610<\/td>\n55.3.6 Detailed functions and state diagrams
55.3.6.1 State diagram conventions
55.3.6.2 State diagram parameters
55.3.6.2.1 Constants
55.3.6.2.2 Variables <\/td>\n<\/tr>\n
613<\/td>\n55.3.6.2.3 Timers
55.3.6.2.4 Functions <\/td>\n<\/tr>\n
615<\/td>\n55.3.6.2.5 Counters
55.3.6.3 Messages
55.3.6.4 State diagrams <\/td>\n<\/tr>\n
616<\/td>\n55.3.7 PCS management
55.3.7.1 Status
55.3.7.2 Counters <\/td>\n<\/tr>\n
623<\/td>\n55.3.7.3 Loopback
55.4 Physical Medium Attachment (PMA) sublayer
55.4.1 PMA functional specifications <\/td>\n<\/tr>\n
624<\/td>\n55.4.2 PMA functions
55.4.2.1 PMA Reset function
55.4.2.2 PMA Transmit function <\/td>\n<\/tr>\n
625<\/td>\n55.4.2.2.1 Alert signal <\/td>\n<\/tr>\n
626<\/td>\n55.4.2.2.2 Link failure signal
55.4.2.3 PMA transmit disable function
55.4.2.3.1 Global PMA transmit disable function
55.4.2.3.2 PMA pair by pair transmit disable function
55.4.2.3.3 PMA MDIO function mapping <\/td>\n<\/tr>\n
627<\/td>\n55.4.2.4 PMA Receive function <\/td>\n<\/tr>\n
628<\/td>\n55.4.2.5 PHY Control function <\/td>\n<\/tr>\n
629<\/td>\n55.4.2.5.1 Infofield notation
55.4.2.5.2 Start of Frame Delimiter
55.4.2.5.3 Current transmitter settings <\/td>\n<\/tr>\n
630<\/td>\n55.4.2.5.4 Next transmitter settings
55.4.2.5.5 Requested transmitter settings
55.4.2.5.6 Message Field <\/td>\n<\/tr>\n
631<\/td>\n55.4.2.5.7 SNR_margin <\/td>\n<\/tr>\n
632<\/td>\n55.4.2.5.8 Transition counter
55.4.2.5.9 Coefficient exchange handshake
55.4.2.5.10 Reserved Fields
55.4.2.5.11 Vendor-specific field
55.4.2.5.12 Coefficient Field
55.4.2.5.13 CRC16 <\/td>\n<\/tr>\n
633<\/td>\n55.4.2.5.14 Startup sequence <\/td>\n<\/tr>\n
636<\/td>\n55.4.2.5.15 Fast retrain function
55.4.2.6 Link Monitor function <\/td>\n<\/tr>\n
637<\/td>\n55.4.2.7 Refresh Monitor function
55.4.2.8 Clock Recovery function
55.4.3 MDI
55.4.3.1 MDI signals transmitted by the PHY <\/td>\n<\/tr>\n
638<\/td>\n55.4.3.2 Signals received at the MDI
55.4.4 Automatic MDI\/MDI-X configuration <\/td>\n<\/tr>\n
639<\/td>\n55.4.5 State variables
55.4.5.1 State diagram variables <\/td>\n<\/tr>\n
642<\/td>\n55.4.5.2 Timers <\/td>\n<\/tr>\n
643<\/td>\n55.4.5.3 Functions
55.4.5.4 Counters <\/td>\n<\/tr>\n
644<\/td>\n55.4.6 State diagrams
55.4.6.1 PHY Control state diagram <\/td>\n<\/tr>\n
645<\/td>\n55.4.6.2 Transition counter state diagrams <\/td>\n<\/tr>\n
647<\/td>\n55.4.6.3 Link Monitor state diagram <\/td>\n<\/tr>\n
648<\/td>\n55.4.6.4 EEE Refresh monitor state diagram <\/td>\n<\/tr>\n
649<\/td>\n55.4.6.5 Fast retrain state diagram
55.5 PMA electrical specifications
55.5.1 Isolation requirement <\/td>\n<\/tr>\n
650<\/td>\n55.5.2 Test modes <\/td>\n<\/tr>\n
652<\/td>\n55.5.2.1 Test fixtures <\/td>\n<\/tr>\n
653<\/td>\n55.5.3 Transmitter electrical specifications
55.5.3.1 Maximum output droop
55.5.3.2 Transmitter linearity. <\/td>\n<\/tr>\n
654<\/td>\n55.5.3.3 Transmitter timing jitter
55.5.3.4 Transmitter power spectral density (PSD) and power level <\/td>\n<\/tr>\n
655<\/td>\n55.5.3.5 Transmit clock frequency
55.5.4 Receiver electrical specifications
55.5.4.1 Receiver differential input signals <\/td>\n<\/tr>\n
656<\/td>\n55.5.4.2 Receiver frequency tolerance
55.5.4.3 Common-mode noise rejection
55.5.4.4 Alien crosstalk noise rejection <\/td>\n<\/tr>\n
657<\/td>\n55.5.4.5 Short reach mode link test
55.5.4.5.1 Short reach test channels
55.6 Management interfaces
55.6.1 Support for Auto-Negotiation <\/td>\n<\/tr>\n
658<\/td>\n55.6.1.1 10GBASE-T use of registers during Auto-Negotiation
55.6.1.2 10GBASE-T Auto-Negotiation page use <\/td>\n<\/tr>\n
660<\/td>\n55.6.1.3 Sending Next Pages
55.6.2 MASTER-SLAVE configuration resolution <\/td>\n<\/tr>\n
662<\/td>\n55.7 Link segment characteristics <\/td>\n<\/tr>\n
663<\/td>\n55.7.1 Cabling system characteristics
55.7.2 Link segment transmission parameters
55.7.2.1 Insertion loss <\/td>\n<\/tr>\n
664<\/td>\n55.7.2.2 Differential characteristic impedance
55.7.2.3 Return loss
55.7.2.4 Coupling parameters between duplex channels comprising one link segment
55.7.2.4.1 Differential near-end crosstalk <\/td>\n<\/tr>\n
665<\/td>\n55.7.2.4.2 Multiple disturber near-end crosstalk (MDNEXT) loss
55.7.2.4.3 Multiple disturber power sum near-end crosstalk (PSNEXT) loss <\/td>\n<\/tr>\n
666<\/td>\n55.7.2.4.4 Equal level far-end crosstalk (ELFEXT) <\/td>\n<\/tr>\n
667<\/td>\n55.7.2.4.5 Multiple disturber equal level far-end crosstalk (MDELFEXT)
55.7.2.4.6 Multiple disturber power sum equal level far-end crosstalk (PS ELFEXT)
55.7.2.5 Maximum link delay
55.7.2.6 Link delay skew
55.7.3 Coupling parameters between link segments <\/td>\n<\/tr>\n
668<\/td>\n55.7.3.1 Multiple disturber alien near-end crosstalk (MDANEXT) loss
55.7.3.1.1 Multiple disturber power sum alien near-end crosstalk (PSANEXT) loss <\/td>\n<\/tr>\n
669<\/td>\n55.7.3.1.2 PSANEXT loss to insertion loss ratio requirements <\/td>\n<\/tr>\n
671<\/td>\n55.7.3.2 Multiple disturber alien far-end crosstalk (MDAFEXT) loss
55.7.3.2.1 Multiple disturber power sum alien equal level far-end crosstalk (PSAELFEXT) <\/td>\n<\/tr>\n
672<\/td>\n55.7.3.2.2 PSAELFEXT to insertion loss ratio requirements <\/td>\n<\/tr>\n
674<\/td>\n55.7.3.3 Alien crosstalk margin computation <\/td>\n<\/tr>\n
678<\/td>\n55.7.4 Noise environment <\/td>\n<\/tr>\n
679<\/td>\n55.8 MDI specification
55.8.1 MDI connectors
55.8.2 MDI electrical specifications <\/td>\n<\/tr>\n
680<\/td>\n55.8.2.1 MDI return loss
55.8.2.2 MDI impedance balance <\/td>\n<\/tr>\n
681<\/td>\n55.8.2.3 MDI fault tolerance <\/td>\n<\/tr>\n
682<\/td>\n55.9 Environmental specifications
55.9.1 General safety
55.9.2 Network safety
55.9.3 Installation and maintenance guidelines <\/td>\n<\/tr>\n
683<\/td>\n55.9.4 Telephone voltages
55.9.5 Electromagnetic compatibility
55.9.6 Temperature and humidity
55.10 PHY labeling
55.11 Delay constraints <\/td>\n<\/tr>\n
685<\/td>\n55.12 Protocol implementation conformance statement (PICS) proforma for Clause 55\u2014Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA) sublayer and baseband medium, type 10GBASE-T
55.12.1 Identification
55.12.1.1 Implementation identification
55.12.1.2 Protocol summary <\/td>\n<\/tr>\n
686<\/td>\n55.12.2 Major capabilities\/options <\/td>\n<\/tr>\n
687<\/td>\n55.12.3 Physical Coding Sublayer (PCS) <\/td>\n<\/tr>\n
689<\/td>\n55.12.3.1 PCS Receive functions
55.12.3.2 Other PCS functions
55.12.4 Physical Medium Attachment (PMA) <\/td>\n<\/tr>\n
691<\/td>\n55.12.5 Management interface <\/td>\n<\/tr>\n
693<\/td>\n55.12.6 PMA Electrical Specifications <\/td>\n<\/tr>\n
694<\/td>\n55.12.7 Characteristics of the link segment <\/td>\n<\/tr>\n
695<\/td>\n55.12.8 MDI requirements
55.12.9 General safety and environmental requirements <\/td>\n<\/tr>\n
696<\/td>\n55.12.10 Timing requirements <\/td>\n<\/tr>\n
697<\/td>\nAnnex 44A (informative) Diagram of Data Flow
44A.1 10GBASE-R bit ordering
44A.2 10GBASE-W serial bit ordering
44A.3 10GBASE-LX4 bit ordering <\/td>\n<\/tr>\n
703<\/td>\n44A.4 Loopback locations <\/td>\n<\/tr>\n
705<\/td>\nAnnex 45A (informative) Clause 45 MDIO electrical interface
45A.1 MDIO driver
45A.2 Single Clause 45 electrical interface <\/td>\n<\/tr>\n
706<\/td>\n45A.3 Clause 45 electrical interface for STA with Clause 22 electrical interface to PHYs
45A.4 Clause 22 electrical interface for STA with Clause 45 electrical interface to MMDs <\/td>\n<\/tr>\n
709<\/td>\nAnnex 48A (normative) Jitter test patterns
48A.1 High-frequency test pattern
48A.2 Low-frequency test pattern
48A.3 Mixed-frequency test pattern <\/td>\n<\/tr>\n
710<\/td>\n48A.4 Continuous random test pattern (CRPAT) <\/td>\n<\/tr>\n
711<\/td>\n48A.5 Continuous jitter test pattern (CJPAT) <\/td>\n<\/tr>\n
712<\/td>\n48A.5.1 Continuous jitter test pattern (CJPAT) 10 bit values <\/td>\n<\/tr>\n
717<\/td>\nAnnex 48B (informative) Jitter test methods
48B.1 BER and jitter model
48B.1.1 Description of dual Dirac mathematical model <\/td>\n<\/tr>\n
719<\/td>\n48B.1.2 Random Jitter
48B.1.3 Addition of Deterministic Jitter
48B.1.4 Effects of jitter high-pass filtering and CJPAT on deterministic jitter <\/td>\n<\/tr>\n
720<\/td>\n48B.2 Jitter tolerance test methodologies
48B.2.1 Calibration of a signal source using the BERT scan technique <\/td>\n<\/tr>\n
721<\/td>\n48B.3 Jitter output test methodologies
48B.3.1 Time domain measurement\u2014Scope and BERT scan
48B.3.1.1 Jitter high pass filtering (using Golden PLL) <\/td>\n<\/tr>\n
722<\/td>\n48B.3.1.2 Time domain scope measurement
48B.3.1.3 BERT Scan
48B.3.1.3.1 Approximate curve-fitting for BERT scan <\/td>\n<\/tr>\n
723<\/td>\n48B.3.2 Time Interval Analysis
48B.3.2.1 TIA with Golden PLL <\/td>\n<\/tr>\n
724<\/td>\n48B.3.2.1.1 Test method <\/td>\n<\/tr>\n
725<\/td>\n48B.3.2.2 TIA with pattern trigger <\/td>\n<\/tr>\n
726<\/td>\n48B.3.2.2.1 Test Method
48B.3.2.3 Approximate curve fitting for TIA bathtub curve <\/td>\n<\/tr>\n
727<\/td>\nAnnex 50A (informative) Thresholds for Severely Errored Second calculations
50A.1 Section SES threshold
50A.2 Line SES threshold
50A.3 Path SES threshold <\/td>\n<\/tr>\n
728<\/td>\n50A.4 Definition of Path Block Error
50A.5 Definition of Far End Path Block Error <\/td>\n<\/tr>\n
729<\/td>\nAnnex 55A (normative) LDPC details
55A.1 The generator matrix
55A.2 The sparse parity check matrix H <\/td>\n<\/tr>\n
730<\/td>\nAnnex 55B (informative) Additional cabling design guidelines for 10GBASE-T
55B.1 Alien crosstalk considerations <\/td>\n<\/tr>\n
731<\/td>\n55B.1.1 Alien crosstalk mitigation <\/td>\n<\/tr>\n
732<\/td>\n55B.1.2 Alien crosstalk mitigation procedure <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":"

IEEE Standard for Ethernet<\/b><\/p>\n\n\n\n\n
Published By<\/td>\nPublication Date<\/td>\nNumber of Pages<\/td>\n<\/tr>\n
IEEE<\/b><\/a><\/td>\n2012<\/td>\n732<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n","protected":false},"featured_media":397814,"template":"","meta":{"rank_math_lock_modified_date":false,"ep_exclude_from_search":false},"product_cat":[2644],"product_tag":[],"class_list":{"0":"post-397807","1":"product","2":"type-product","3":"status-publish","4":"has-post-thumbnail","6":"product_cat-ieee","8":"first","9":"instock","10":"sold-individually","11":"shipping-taxable","12":"purchasable","13":"product-type-simple"},"_links":{"self":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product\/397807","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product"}],"about":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/types\/product"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media\/397814"}],"wp:attachment":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media?parent=397807"}],"wp:term":[{"taxonomy":"product_cat","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_cat?post=397807"},{"taxonomy":"product_tag","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_tag?post=397807"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}