IEEE 1364 2006

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IEEE Standard for Verilog Hardware Description Language

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IEEE	2006	590

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Description

Revision Standard – Inactive – Superseded. The Verilog hardware description language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine-readable and human-readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. The primary audiences for this standard are the implementers of tools supporting the language and advanced users of the language.

PDF Catalog

PDF Pages	PDF Title
3	IEEE Standard for Verilog® Hardware Description Language
5	Introduction
6	Notice to users Errata Interpretations Patents Participants
9	Contents
23	List of Figures
25	List of Tables
28	List of Syntax Boxes
31	IEEE Standard for Verilog® Hardware Description Language 1. Overview 1.1 Scope 1.2 Conventions used in this standard
32	1.3 Syntactic description
33	1.4 Use of color in this standard 1.5 Contents of this standard
35	1.6 Deprecated clauses 1.7 Header file listings 1.8 Examples 1.9 Prerequisites
36	2. Normative references
38	3. Lexical conventions 3.1 Lexical tokens 3.2 White space 3.3 Comments 3.4 Operators
39	3.5 Numbers
40	3.5.1 Integer constants
42	3.5.2 Real constants 3.5.3 Conversion 3.6 Strings
43	3.6.1 String variable declaration 3.6.2 String manipulation 3.6.3 Special characters in strings
44	3.7 Identifiers, keywords, and system names 3.7.1 Escaped identifiers
45	3.7.2 Keywords 3.7.3 System tasks and functions 3.7.4 Compiler directives
46	3.8 Attributes 3.8.1 Examples
48	3.8.2 Syntax
51	4. Data types 4.1 Value set 4.2 Nets and variables 4.2.1 Net declarations
53	4.2.2 Variable declarations
54	4.3 Vectors 4.3.1 Specifying vectors 4.3.2 Vector net accessibility
55	4.4 Strengths 4.4.1 Charge strength 4.4.2 Drive strength 4.5 Implicit declarations
56	4.6 Net types 4.6.1 Wire and tri nets
57	4.6.2 Wired nets
58	4.6.3 Trireg net
61	4.6.4 Tri0 and tri1 nets 4.6.5 Unresolved nets
62	4.6.6 Supply nets 4.7 Regs 4.8 Integers, reals, times, and realtimes
63	4.8.1 Operators and real numbers 4.8.2 Conversion
64	4.9 Arrays 4.9.1 Net arrays 4.9.2 reg and variable arrays
65	4.9.3 Memories 4.10 Parameters
66	4.10.1 Module parameters
67	4.10.2 Local parameters (localparam)
68	4.10.3 Specify parameters
69	4.11 Name spaces
71	5. Expressions 5.1 Operators
72	5.1.1 Operators with real operands
73	5.1.2 Operator precedence
74	5.1.3 Using integer numbers in expressions
75	5.1.4 Expression evaluation order 5.1.5 Arithmetic operators
77	5.1.6 Arithmetic expressions with regs and integers
78	5.1.7 Relational operators
79	5.1.8 Equality operators 5.1.9 Logical operators
80	5.1.10 Bitwise operators
81	5.1.11 Reduction operators
83	5.1.12 Shift operators 5.1.13 Conditional operator
84	5.1.14 Concatenations
85	5.2 Operands
86	5.2.1 Vector bit-select and part-select addressing
87	5.2.2 Array and memory addressing
88	5.2.3 Strings
91	5.3 Minimum, typical, and maximum delay expressions
92	5.4 Expression bit lengths 5.4.1 Rules for expression bit lengths
93	5.4.2 Example of expression bit-length problem
94	5.4.3 Example of self-determined expressions 5.5 Signed expressions
95	5.5.1 Rules for expression types 5.5.2 Steps for evaluating an expression
96	5.5.3 Steps for evaluating an assignment 5.5.4 Handling X and Z in signed expressions 5.6 Assignments and truncation
98	6. Assignments 6.1 Continuous assignments
99	6.1.1 The net declaration assignment 6.1.2 The continuous assignment statement
101	6.1.3 Delays 6.1.4 Strength
102	6.2 Procedural assignments 6.2.1 Variable declaration assignment
103	6.2.2 Variable declaration syntax
104	7. Gate- and switch-level modeling 7.1 Gate and switch declaration syntax
106	7.1.1 The gate type specification 7.1.2 The drive strength specification
107	7.1.3 The delay specification 7.1.4 The primitive instance identifier 7.1.5 The range specification
108	7.1.6 Primitive instance connection list
110	7.2 and, nand, nor, or, xor, and xnor gates
111	7.3 buf and not gates
112	7.4 bufif1, bufif0, notif1, and notif0 gates
113	7.5 MOS switches
114	7.6 Bidirectional pass switches
115	7.7 CMOS switches
116	7.8 pullup and pulldown sources 7.9 Logic strength modeling
118	7.10 Strengths and values of combined signals 7.10.1 Combined signals of unambiguous strength
119	7.10.2 Ambiguous strengths: sources and combinations
124	7.10.3 Ambiguous strength signals and unambiguous signals
128	7.10.4 Wired logic net types
130	7.11 Strength reduction by nonresistive devices 7.12 Strength reduction by resistive devices 7.13 Strengths of net types 7.13.1 tri0 and tri1 net strengths 7.13.2 trireg strength
131	7.13.3 supply0 and supply1 net strengths 7.14 Gate and net delays
132	7.14.1 min:typ:max delays
133	7.14.2 trireg net charge decay
135	8. User-defined primitives (UDPs) 8.1 UDP definition
137	8.1.1 UDP header 8.1.2 UDP port declarations 8.1.3 Sequential UDP initial statement 8.1.4 UDP state table
138	8.1.5 Z values in UDP 8.1.6 Summary of symbols
139	8.2 Combinational UDPs
140	8.3 Level-sensitive sequential UDPs 8.4 Edge-sensitive sequential UDPs
141	8.5 Sequential UDP initialization
143	8.6 UDP instances
144	8.7 Mixing level-sensitive and edge-sensitive descriptions
145	8.8 Level-sensitive dominance
146	9. Behavioral modeling 9.1 Behavioral model overview
147	9.2 Procedural assignments 9.2.1 Blocking procedural assignments
148	9.2.2 The nonblocking procedural assignment
152	9.3 Procedural continuous assignments
153	9.3.1 The assign and deassign procedural statements
154	9.3.2 The force and release procedural statements
155	9.4 Conditional statement
156	9.4.1 If-else-if construct
157	9.5 Case statement
158	9.5.1 Case statement with do-not-cares
159	9.5.2 Constant expression in case statement
160	9.6 Looping statements
161	9.7 Procedural timing controls
162	9.7.1 Delay control 9.7.2 Event control
163	9.7.3 Named events
164	9.7.4 Event or operator 9.7.5 Implicit event_expression list
166	9.7.6 Level-sensitive event control 9.7.7 Intra-assignment timing controls
169	9.8 Block statements
170	9.8.1 Sequential blocks
171	9.8.2 Parallel blocks 9.8.3 Block names
172	9.8.4 Start and finish times
173	9.9 Structured procedures 9.9.1 Initial construct
174	9.9.2 Always construct
175	10. Tasks and functions 10.1 Distinctions between tasks and functions 10.2 Tasks and task enabling
176	10.2.1 Task declarations
177	10.2.2 Task enabling and argument passing
179	10.2.3 Task memory usage and concurrent activation
180	10.3 Disabling of named blocks and tasks
182	10.4 Functions and function calling 10.4.1 Function declarations
184	10.4.2 Returning a value from a function
185	10.4.3 Calling a function 10.4.4 Function rules
186	10.4.5 Use of constant functions
188	11. Scheduling semantics 11.1 Execution of a model 11.2 Event simulation 11.3 The stratified event queue
189	11.4 Verilog simulation reference model
190	11.4.1 Determinism 11.4.2 Nondeterminism 11.5 Race conditions
191	11.6 Scheduling implication of assignments 11.6.1 Continuous assignment 11.6.2 Procedural continuous assignment 11.6.3 Blocking assignment 11.6.4 Nonblocking assignment 11.6.5 Switch (transistor) processing
192	11.6.6 Port connections 11.6.7 Functions and tasks
193	12. Hierarchical structures 12.1 Modules
195	12.1.1 Top-level modules 12.1.2 Module instantiation
197	12.2 Overriding module parameter values
198	12.2.1 defparam statement
200	12.2.2 Module instance parameter value assignment
203	12.2.3 Parameter dependence 12.3 Ports 12.3.1 Port definition
204	12.3.2 List of ports 12.3.3 Port declarations
206	12.3.4 List of ports declarations 12.3.5 Connecting module instance ports by ordered list
207	12.3.6 Connecting module instance ports by name
208	12.3.7 Real numbers in port connections 12.3.8 Connecting dissimilar ports
209	12.3.9 Port connection rules 12.3.10 Net types resulting from dissimilar port connections
211	12.3.11 Connecting signed values via ports 12.4 Generate constructs
213	12.4.1 Loop generate constructs
216	12.4.2 Conditional generate constructs
220	12.4.3 External names for unnamed generate blocks
221	12.5 Hierarchical names
223	12.6 Upwards name referencing
225	12.7 Scope rules
227	12.8 Elaboration 12.8.1 Order of elaboration 12.8.2 Early resolution of hierarchical names
229	13. Configuring the contents of a design 13.1 Introduction 13.1.1 Library notation
230	13.1.2 Basic configuration elements 13.2 Libraries 13.2.1 Specifying libraries-the library map file
232	13.2.2 Using multiple library map files 13.2.3 Mapping source files to libraries 13.3 Configurations 13.3.1 Basic configuration syntax
235	13.3.2 Hierarchical configurations 13.4 Using libraries and configs 13.4.1 Precompiling in a single-pass use model
236	13.4.2 Elaboration-time compiling in a single-pass use model 13.4.3 Precompiling using a separate compilation tool 13.4.4 Command line considerations 13.5 Configuration examples
237	13.5.1 Default configuration from library map file 13.5.2 Using default clause 13.5.3 Using cell clause
238	13.5.4 Using instance clause 13.5.5 Using hierarchical config 13.6 Displaying library binding information
239	13.7 Library mapping examples 13.7.1 Using the command line to control library searching 13.7.2 File path specification examples 13.7.3 Resolving multiple path specifications
241	14. Specify blocks 14.1 Specify block declaration
242	14.2 Module path declarations
243	14.2.1 Module path restrictions 14.2.2 Simple module paths
244	14.2.3 Edge-sensitive paths
245	14.2.4 State-dependent paths
249	14.2.5 Full connection and parallel connection paths
250	14.2.6 Declaring multiple module paths in a single statement 14.2.7 Module path polarity
252	14.3 Assigning delays to module paths 14.3.1 Specifying transition delays on module paths
254	14.3.2 Specifying x transition delays
255	14.3.3 Delay selection 14.4 Mixing module path delays and distributed delays
256	14.5 Driving wired logic
258	14.6 Detailed control of pulse filtering behavior
259	14.6.1 Specify block control of pulse limit values
260	14.6.2 Global control of pulse limit values 14.6.3 SDF annotation of pulse limit values 14.6.4 Detailed pulse control capabilities
267	15. Timing checks 15.1 Overview
270	15.2 Timing checks using a stability window
271	15.2.1 $setup
272	15.2.2 $hold
273	15.2.3 $setuphold
275	15.2.4 $removal
276	15.2.5 $recovery
277	15.2.6 $recrem
278	15.3 Timing checks for clock and control signals
279	15.3.1 $skew
280	15.3.2 $timeskew
282	15.3.3 $fullskew
285	15.3.4 $width
286	15.3.5 $period
287	15.3.6 $nochange
288	15.4 Edge-control specifiers
289	15.5 Notifiers: user-defined responses to timing violations
291	15.5.1 Requirements for accurate simulation
293	15.5.2 Conditions in negative timing checks
294	15.5.3 Notifiers in negative timing checks 15.5.4 Option behavior
295	15.6 Enabling timing checks with conditioned events
296	15.7 Vector signals in timing checks 15.8 Negative timing checks
299	16. Backannotation using the standard delay format (SDF) 16.1 The SDF annotator 16.2 Mapping of SDF constructs to Verilog 16.2.1 Mapping of SDF delay constructs to Verilog declarations
301	16.2.2 Mapping of SDF timing check constructs to Verilog
302	16.2.3 SDF annotation of specparams
303	16.2.4 SDF annotation of interconnect delays
304	16.3 Multiple annotations
305	16.4 Multiple SDF files 16.5 Pulse limit annotation
306	16.6 SDF to Verilog delay value mapping
307	17. System tasks and functions
308	17.1 Display system tasks 17.1.1 The display and write tasks
315	17.1.2 Strobed monitoring
316	17.1.3 Continuous monitoring 17.2 File input-output system tasks and functions
317	17.2.1 Opening and closing files
318	17.2.2 File output system tasks
319	17.2.3 Formatting data to a string
320	17.2.4 Reading data from a file
324	17.2.5 File positioning
325	17.2.6 Flushing output 17.2.7 I/O error status 17.2.8 Detecting EOF
326	17.2.9 Loading memory data from a file
327	17.2.10 Loading timing data from an SDF file
328	17.3 Timescale system tasks
329	17.3.1 $printtimescale
330	17.3.2 $timeformat
332	17.4 Simulation control system tasks 17.4.1 $finish 17.4.2 $stop
333	17.5 Programmable logic array (PLA) modeling system tasks 17.5.1 Array types
334	17.5.2 Array logic types 17.5.3 Logic array personality declaration and loading 17.5.4 Logic array personality formats
337	17.6 Stochastic analysis tasks 17.6.1 $q_initialize 17.6.2 $q_add 17.6.3 $q_remove
338	17.6.4 $q_full 17.6.5 $q_exam 17.6.6 Status codes
339	17.7 Simulation time system functions 17.7.1 $time 17.7.2 $stime
340	17.7.3 $realtime 17.8 Conversion functions
341	17.9 Probabilistic distribution functions 17.9.1 $random function
342	17.9.2 $dist_ functions
343	17.9.3 Algorithm for probabilistic distribution functions
350	17.10 Command line input 17.10.1 $test$plusargs (string)
351	17.10.2 $value$plusargs (user_string, variable)
353	17.11 Math functions 17.11.1 Integer math functions 17.11.2 Real math functions
355	18. Value change dump (VCD) files 18.1 Creating four-state VCD file 18.1.1 Specifying name of dump file ($dumpfile)
356	18.1.2 Specifying variables to be dumped ($dumpvars)
357	18.1.3 Stopping and resuming the dump ($dumpoff/$dumpon)
358	18.1.4 Generating a checkpoint ($dumpall) 18.1.5 Limiting size of dump file ($dumplimit) 18.1.6 Reading dump file during simulation ($dumpflush)
359	18.2 Format of four-state VCD file
360	18.2.1 Syntax of four-state VCD file
361	18.2.2 Formats of variable values
362	18.2.3 Description of keyword commands
367	18.2.4 Four-state VCD file format example
368	18.3 Creating extended VCD file 18.3.1 Specifying dump file name and ports to be dumped ($dumpports)
369	18.3.2 Stopping and resuming the dump ($dumpportsoff/$dumpportson)
370	18.3.3 Generating a checkpoint ($dumpportsall) 18.3.4 Limiting size of dump file ($dumpportslimit)
371	18.3.5 Reading dump file during simulation ($dumpportsflush) 18.3.6 Description of keyword commands 18.3.7 General rules for extended VCD system tasks
372	18.4 Format of extended VCD file 18.4.1 Syntax of extended VCD file
374	18.4.2 Extended VCD node information
376	18.4.3 Value changes
377	18.4.4 Extended VCD file format example
379	19. Compiler directives 19.1 `celldefine and `endcelldefine 19.2 `default_nettype
380	19.3 `define and `undef 19.3.1 `define
382	19.3.2 `undef 19.4 `ifdef, `else, `elsif, `endif, `ifndef
386	19.5 `include 19.6 `resetall
387	19.7 `line
388	19.8 `timescale
390	19.9 `unconnected_drive and `nounconnected_drive 19.10 `pragma
391	19.10.1 Standard pragmas 19.11 `begin_keywords, `end_keywords
396	20. Programming language interface (PLI) overview 20.1 PLI purpose and history
397	20.2 User-defined system task/function names 20.3 User-defined system task/function types 20.4 Overriding built-in system task/function names 20.5 User-supplied PLI applications
398	20.6 PLI mechanism 20.7 User-defined system task/function arguments 20.8 PLI include files
399	21. PLI TF and ACC interface mechanism (deprecated)
400	22. Using ACC routines (deprecated)
401	23. ACC routine definitions (deprecated)
402	24. Using TF routines (deprecated)
403	25. TF routine definitions (deprecated)
404	26. Using Verilog procedural interface (VPI) routines 26.1 VPI system tasks and functions 26.1.1 sizetf VPI application routine 26.1.2 compiletf VPI application routine
405	26.1.3 calltf VPI application routine 26.1.4 Arguments to sizetf, compiletf, and calltf application routines 26.2 VPI mechanism 26.2.1 VPI callbacks
406	26.2.2 VPI access to Verilog HDL objects and simulation objects 26.2.3 Error handling 26.2.4 Function availability
407	26.2.5 Traversing expressions 26.3 VPI object classifications
408	26.3.1 Accessing object relationships and properties
409	26.3.2 Object type properties
410	26.3.3 Object file and line properties 26.3.4 Delays and values
411	26.3.5 Object protection properties 26.4 List of VPI routines by functional category
413	26.5 Key to data model diagrams
414	26.5.1 Diagram key for objects and classes 26.5.2 Diagram key for accessing properties
415	26.5.3 Diagram key for traversing relationships
416	26.6 Object data model diagrams
417	26.6.1 Module
418	26.6.2 Instance arrays
419	26.6.3 Scope 26.6.4 IO declaration
420	26.6.5 Ports
421	26.6.6 Nets and net arrays
423	26.6.7 Regs and reg arrays
425	26.6.8 Variables
426	26.6.9 Memory 26.6.10 Object range
427	26.6.11 Named event
428	26.6.12 Parameter, specparam
429	26.6.13 Primitive, prim term
430	26.6.14 UDP
431	26.6.15 Module path, path term 26.6.16 Intermodule path
432	26.6.17 Timing check 26.6.18 Task, function declaration
433	26.6.19 Task/function call
434	26.6.20 Frames
435	26.6.21 Delay terminals 26.6.22 Net drivers and loads
436	26.6.23 Reg drivers and loads 26.6.24 Continuous assignment
437	26.6.25 Simple expressions
438	26.6.26 Expressions
439	26.6.27 Process, block, statement, event statement
440	26.6.28 Assignment 26.6.29 Delay control 26.6.30 Event control
441	26.6.31 Repeat control 26.6.32 While, repeat, wait 26.6.33 For 26.6.34 Forever
442	26.6.35 If, if-else 26.6.36 Case
443	26.6.37 Assign statement, deassign, force, release 26.6.38 Disable
444	26.6.39 Callback 26.6.40 Time queue 26.6.41 Active time format
445	26.6.42 Attributes
446	26.6.43 Iterator
447	26.6.44 Generates
448	27. VPI routine definitions 27.1 vpi_chk_error()
450	27.2 vpi_compare_objects() 27.3 vpi_control()
451	27.4 vpi_flush() 27.5 vpi_free_object()
452	27.6 vpi_get() 27.7 vpi_get_cb_info()
453	27.8 vpi_get_data()
454	27.9 vpi_get_delays()
456	27.10 vpi_get_str()
457	27.11 vpi_get_systf_info()
458	27.12 vpi_get_time()
459	27.13 vpi_get_userdata() 27.14 vpi_get_value()
465	27.15 vpi_get_vlog_info()
466	27.16 vpi_handle()
467	27.17 vpi_handle_by_index()
468	27.18 vpi_handle_by_multi_index() 27.19 vpi_handle_by_name()
469	27.20 vpi_handle_multi() 27.21 vpi_iterate()
470	27.22 vpi_mcd_close()
471	27.23 vpi_mcd_flush() 27.24 vpi_mcd_name()
472	27.25 vpi_mcd_open()
473	27.26 vpi_mcd_printf()
474	27.27 vpi_mcd_vprintf() 27.28 vpi_printf()
475	27.29 vpi_put_data()
477	27.30 vpi_put_delays()
480	27.31 vpi_put_userdata() 27.32 vpi_put_value()
483	27.33 vpi_register_cb()
484	27.33.1 Simulation event callbacks
488	27.33.2 Simulation time callbacks
490	27.33.3 Simulator action or feature callbacks
491	27.34 vpi_register_systf()
492	27.34.1 System task/function callbacks
493	27.34.2 Initializing VPI system task/function callbacks
494	27.34.3 Registering multiple system tasks and functions
495	27.35 vpi_remove_cb() 27.36 vpi_scan()
496	27.37 vpi_vprintf()
497	28. Protected envelopes 28.1 General 28.2 Processing protected envelopes
498	28.2.1 Encryption
499	28.2.2 Decryption 28.3 Protect pragma directives
501	28.4 Protect pragma keywords 28.4.1 begin 28.4.2 end 28.4.3 begin_protected
502	28.4.4 end_protected 28.4.5 author
503	28.4.6 author_info 28.4.7 encrypt_agent 28.4.8 encrypt_agent_info
504	28.4.9 encoding
505	28.4.10 data_keyowner 28.4.11 data_method
506	28.4.12 data_keyname
507	28.4.13 data_public_key 28.4.14 data_decrypt_key
508	28.4.15 data_block 28.4.16 digest_keyowner 28.4.17 digest_key_method
509	28.4.18 digest_keyname 28.4.19 digest_public_key
510	28.4.20 digest_decrypt_key 28.4.21 digest_method
511	28.4.22 digest_block
512	28.4.23 key_keyowner 28.4.24 key_method 28.4.25 key_keyname
513	28.4.26 key_public_key 28.4.27 key_block
514	28.4.28 decrypt_license 28.4.29 runtime_license
515	28.4.30 comment 28.4.31 reset
516	28.4.32 viewport
517	Annex A (normative) Formal syntax definition A.1 Source text A.1.1 Library source text A.1.2 Verilog source text A.1.3 Module parameters and ports
518	A.1.4 Module items
519	A.1.5 Configuration source text A.2 Declarations A.2.1 Declaration types
520	A.2.2 Declaration data types
521	A.2.3 Declaration lists A.2.4 Declaration assignments
522	A.2.5 Declaration ranges A.2.6 Function declarations A.2.7 Task declarations
523	A.2.8 Block item declarations A.3 Primitive instances A.3.1 Primitive instantiation and instances
524	A.3.2 Primitive strengths A.3.3 Primitive terminals A.3.4 Primitive gate and switch types
525	A.4 Module instantiation and generate construct A.4.1 Module instantiation A.4.2 Generate construct
526	A.5 UDP declaration and instantiation A.5.1 UDP declaration A.5.2 UDP ports A.5.3 UDP body
527	A.5.4 UDP instantiation A.6 Behavioral statements A.6.1 Continuous assignment statements A.6.2 Procedural blocks and assignments A.6.3 Parallel and sequential blocks
528	A.6.4 Statements A.6.5 Timing control statements
529	A.6.6 Conditional statements A.6.7 Case statements A.6.8 Looping statements A.6.9 Task enable statements
530	A.7 Specify section A.7.1 Specify block declaration A.7.2 Specify path declarations A.7.3 Specify block terminals A.7.4 Specify path delays
532	A.7.5 System timing checks
534	A.8 Expressions A.8.1 Concatenations A.8.2 Function calls A.8.3 Expressions
535	A.8.4 Primaries
536	A.8.5 Expression left-side values A.8.6 Operators A.8.7 Numbers
537	A.8.8 Strings A.9 General A.9.1 Attributes
538	A.9.2 Comments A.9.3 Identifiers
539	A.9.4 White space
540	Annex B (normative) List of keywords
541	Annex C (informative) System tasks and functions C.1 $countdrivers
542	C.2 $getpattern
543	C.3 $input C.4 $key and $nokey C.5 $list
544	C.6 $log and $nolog C.7 $reset, $reset_count, and $reset_value
545	C.8 $save, $restart, and $incsave
546	C.9 $scale C.10 $scope C.11 $showscopes C.12 $showvars
547	C.13 $sreadmemb and $sreadmemh
548	Annex D (informative) Compiler directives D.1 `default_decay_time D.2 `default_trireg_strength
549	D.3 `delay_mode_distributed D.4 `delay_mode_path D.5 `delay_mode_unit D.6 `delay_mode_zero
550	Annex E (normative) acc_user.h (deprecated)
551	Annex F (normative) veriuser.h (deprecated)
552	Annex G (normative) vpi_user.h
567	Annex H (informative) Encryption/decryption flow H.1 Tool vendor secret key encryption system H.1.1 Encryption input
568	H.1.2 Encryption output H.2 IP author secret key encryption system H.2.1 Encryption input
569	H.2.2 Encryption output H.3 Digital envelopes
570	H.3.1 Encryption input
571	H.3.2 Encryption output
572	Annex I (informative) Bibliography
573	Index