Revision Standard – Active. VHSIC Hardware Description Language (VHDL) is defined. VHDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. Its primary audiences are the implementors of tools supporting the language and the advanced users of the language. (This standard incorporates open source. See https://opensource.ieee.org/vasg/Packages)

PDF Catalog

PDF Pages	PDF Title
1	IEEE Std 1076-2019 Front cover
2	Title page
4	Important Notices and Disclaimers Concerning IEEE Standards Documents
7	Participants
8	Introduction Acknowledgments
9	Contents
15	1. Overview 1.1 Scope 1.2 Purpose 1.3 Structure and terminology of this standard 1.3.1 General
16	1.3.2 Syntactic description 1.3.3 Semantic description
17	1.3.4 Front matter, examples, notes, references, and annexes 1.3.5 Incorporation of Property Specification Language 1.4 Word usage
19	2. Normative references
20	3. Design entities and configurations 3.1 General 3.2 Entity declarations 3.2.1 General
21	3.2.2 Entity header 3.2.3 Entity declarative part
22	3.2.4 Entity statement part
23	3.3 Architecture bodies 3.3.1 General
24	3.3.2 Architecture declarative part
25	3.3.3 Architecture statement part
26	3.4 Configuration declarations 3.4.1 General
27	3.4.2 Block configuration
30	3.4.3 Component configuration
33	4. Subprograms and packages 4.1 General 4.2 Subprogram declarations 4.2.1 General
35	4.2.2 Formal parameters 4.2.2.1 Formal parameter lists
36	4.2.2.2 Constant and variable parameters
37	4.2.2.3 Signal parameters 4.2.2.4 File parameters
38	4.3 Subprogram bodies
40	4.4 Subprogram instantiation declarations
41	4.5 Subprogram overloading 4.5.1 General
42	4.5.2 Operator overloading
43	4.5.3 Signatures
44	4.6 Resolution functions
45	4.7 Package declarations
46	4.8 Package bodies
48	4.9 Package instantiation declarations
49	4.10 Conformance rules
50	5. Types 5.1 General
51	5.2 Scalar types 5.2.1 General
52	5.2.2 Enumeration types 5.2.2.1 General
53	5.2.2.2 Predefined enumeration types 5.2.3 Integer types 5.2.3.1 General
54	5.2.3.2 Predefined integer types 5.2.4 Physical types 5.2.4.1 General
56	5.2.4.2 Predefined physical types
57	5.2.5 Floating-point types 5.2.5.1 General 5.2.5.2 Predefined floating-point types
58	5.2.6 Predefined operations on scalar types
59	5.3 Composite types 5.3.1 General
60	5.3.2 Array types 5.3.2.1 General
62	5.3.2.2 Index constraints and discrete ranges
65	5.3.2.3 Predefined array types 5.3.2.4 Predefined operations on array types
66	5.3.3 Record types 5.3.3.1 General
68	5.3.3.2 Predefined record types 5.3.3.3 Predefined operations on record types
69	5.4 Access types 5.4.1 General
70	5.4.2 Incomplete type declarations
71	5.4.3 Allocation and deallocation of objects 5.5 File types 5.5.1 General
72	5.5.2 File operations
76	5.6 Protected types 5.6.1 Protected type definitions 5.6.2 Protected type declarations
78	5.6.3 Protected type bodies
80	5.6.4 Protected type instantiation 5.7 String representations
82	5.8 Unspecified types 5.8.1 General
83	5.8.2 Private incomplete type 5.8.3 Scalar incomplete type 5.8.4 Discrete incomplete type 5.8.5 Integer incomplete type
84	5.8.6 Physical incomplete type 5.8.7 Floating incomplete type 5.8.8 Array incomplete type 5.8.9 Access incomplete type
85	5.8.10 File incomplete type
86	6. Declarations 6.1 General
87	6.2 Type declarations 6.3 Subtype declarations
89	6.4 Objects 6.4.1 General
90	6.4.2 Object declarations 6.4.2.1 General 6.4.2.2 Constant declarations
91	6.4.2.3 Signal declarations
93	6.4.2.4 Variable declarations
95	6.4.2.5 File declarations
97	6.5 Interface declarations 6.5.1 General 6.5.2 Interface object declarations
102	6.5.3 Interface type declarations 6.5.3.1 General 6.5.3.2 Array interface type declaration
103	6.5.3.3 Access interface type declaration
104	6.5.3.4 File interface type declaration
105	6.5.4 Interface subprogram declarations
106	6.5.5 Interface package declarations
107	6.5.6 Interface lists 6.5.6.1 General 6.5.6.2 Generic clauses
108	6.5.6.3 Port clauses
110	6.5.7 Association lists 6.5.7.1 General
114	6.5.7.2 Generic map aspects
119	6.5.7.3 Port map aspects
120	6.6 Alias declarations
121	6.6.1 Object aliases
122	6.6.2 Nonobject aliases
123	6.7 Attribute declarations
124	6.8 Component declarations 6.9 Group template declarations
125	6.10 Group declarations 6.11 PSL clock declarations
127	7. Specifications 7.1 General 7.2 Attribute specification
130	7.3 Configuration specification 7.3.1 General
131	7.3.2 Binding indication 7.3.2.1 General
133	7.3.2.2 Entity aspect
134	7.3.3 Default binding indication
135	7.3.4 Verification unit binding indication
136	7.4 Disconnection specification
139	8. Names 8.1 General
140	8.2 Simple names
141	8.3 Selected names
143	8.4 Indexed names
144	8.5 Slice names 8.6 Attribute names
145	8.7 External names
149	9. Expressions 9.1 General
150	9.2 Operators 9.2.1 General
151	9.2.2 Logical operators
153	9.2.3 Relational operators
156	9.2.4 Shift operators
157	9.2.5 Adding operators
159	9.2.6 Sign operators
160	9.2.7 Multiplying operators
162	9.2.8 Miscellaneous operators 9.2.9 Condition operator
164	9.3 Operands 9.3.1 General 9.3.2 Literals
165	9.3.3 Aggregates 9.3.3.1 General
166	9.3.3.2 Record aggregates 9.3.3.3 Array aggregates
168	9.3.4 Function calls
169	9.3.5 Qualified expressions 9.3.6 Type conversions
171	9.3.7 Allocators
173	9.4 Static expressions 9.4.1 General 9.4.2 Locally static primaries
174	9.4.3 Globally static primaries
176	9.5 Universal expressions
177	10. Sequential statements 10.1 General 10.2 Wait statement
179	10.3 Assertion statement
180	10.4 Report statement
181	10.5 Signal assignment statement 10.5.1 General 10.5.2 Simple signal assignments 10.5.2.1 General
184	10.5.2.2 Executing a simple assignment statement
187	10.5.3 Conditional signal assignments
188	10.5.4 Selected signal assignments
190	10.6 Variable assignment statement 10.6.1 General 10.6.2 Simple variable assignments 10.6.2.1 General
192	10.6.3 Selected variable assignments 10.7 Procedure call statement
193	10.8 If statement
194	10.9 Case statement
196	10.10 Loop statement
197	10.11 Next statement 10.12 Exit statement 10.13 Return statement
198	10.14 Null statement 10.15 Sequential block statement
200	11. Concurrent statements 11.1 General 11.2 Block statement
201	11.3 Process statement
203	11.4 Concurrent procedure call statements
204	11.5 Concurrent assertion statements
205	11.6 Concurrent signal assignment statements
207	11.7 Component instantiation statements 11.7.1 General
208	11.7.2 Instantiation of a component
210	11.7.3 Instantiation of a design entity
213	11.8 Generate statements
217	12. Scope and visibility 12.1 Declarative region 12.2 Scope of declarations
219	12.3 Visibility
223	12.4 Use clauses
224	12.5 The context of overload resolution
226	13. Design units and their analysis 13.1 Design units 13.2 Design libraries
228	13.3 Context declarations 13.4 Context clauses
229	13.5 Order of analysis
230	14. Elaboration and execution 14.1 General 14.2 Elaboration of a design hierarchy
233	14.3 Elaboration of a block, package, subprogram or protected type header 14.3.1 General
234	14.3.2 Generic clause 14.3.3 Generic map aspect 14.3.3.1 General 14.3.3.2 Association elements for generic constants 14.3.3.3 Association elements for generic types
235	14.3.3.4 Association elements for generic subprograms 14.3.3.5 Association elements for generic packages 14.3.4 Port clause 14.3.5 Port map aspect
236	14.4 Elaboration of a declarative part 14.4.1 General
237	14.4.2 Elaboration of a declaration 14.4.2.1 General 14.4.2.2 Subprogram declarations, bodies, and instantiations
238	14.4.2.3 Type declarations and instantiations
239	14.4.2.4 Subtype declarations 14.4.2.5 Object declarations
240	14.4.2.6 Elaboration of a mode view declaration 14.4.2.7 Alias declarations 14.4.2.8 Attribute declarations 14.4.2.9 Component declarations 14.4.2.10 Packages
241	14.4.3 Elaboration of a specification 14.4.3.1 General 14.4.3.2 Attribute specifications 14.4.3.3 Configuration specifications
242	14.4.3.4 Disconnection specifications 14.5 Elaboration of a statement part 14.5.1 General 14.5.2 Block statements
243	14.5.3 Generate statements
244	14.5.4 Component instantiation statements
245	14.5.5 Other concurrent statements 14.6 Dynamic elaboration
246	14.7 Execution of a model 14.7.1 General
247	14.7.2 Drivers 14.7.3 Propagation of signal values 14.7.3.1 General
248	14.7.3.2 Driving values
249	14.7.3.3 Effective values
250	14.7.3.4 Signal update
251	14.7.4 Updating implicit signals
253	14.7.5 Model execution 14.7.5.1 General 14.7.5.2 Initialization
254	14.7.5.3 Simulation cycle
257	15. Lexical elements 15.1 General 15.2 Character set
259	15.3 Lexical elements, separators, and delimiters
261	15.4 Identifiers 15.4.1 General 15.4.2 Basic identifiers 15.4.3 Extended identifiers
262	15.5 Abstract literals 15.5.1 General 15.5.2 Decimal literals 15.5.3 Based literals
263	15.6 Character literals 15.7 String literals
264	15.8 Bit string literals
267	15.9 Comments 15.10 Reserved words
269	15.11 Tool directives
270	16. Predefined language environment 16.1 General 16.2 Predefined attributes 16.2.1 General
271	16.2.2 Predefined attributes of types and objects
276	16.2.3 Predefined attributes of arrays
278	16.2.4 Predefined attributes of signals
280	16.2.5 Predefined attributes of named entities
287	16.2.6 Predefined attributes of ranges 16.2.7 Predefined attributes of PSL Objects
288	16.2.8 Predefined attributes of named mode views 16.3 Package STANDARD
306	16.4 Package TEXTIO
312	16.5 Standard environment package 16.5.1 General 16.5.2 Package declaration
319	16.5.3 Simulator API
320	16.5.4 Date and time API
321	16.5.5 Directory API
322	16.5.6 Environment API
323	16.5.7 Current file and line API
324	16.5.8 PSL API 16.5.9 Report and assert statement API
326	16.6 Standard mathematical packages
327	16.7 Standard multivalue logic package 16.8 Standard synthesis packages
328	16.8.1 Overview 16.8.1.1 Scope 16.8.1.2 Terminology 16.8.2 Interpretation of the standard logic types 16.8.2.1 General 16.8.2.2 The STD_LOGIC_1164 values
329	16.8.2.3 Static constant values 16.8.2.4 Interpretation of logic values 16.8.2.4.1 General 16.8.2.4.2 Interpretation of the forcing and weak values (‘0’, ‘1’, ‘L’, ‘H’, FALSE, TRUE) 16.8.2.4.3 Interpretation of the metalogical values (‘U’, ‘W’, ‘X’, ‘–’) 16.8.2.4.3.1 Metalogical values in relational expressions
330	16.8.2.4.3.3 Metalogical values in logical, arithmetic, and shift operations 16.8.2.4.3.4 Metalogical values in concatenate operations 16.8.2.4.3.5 Metalogical values in type conversion and sign-extension functions 16.8.2.4.3.6 Metalogical values used in assignment references 16.8.2.4.4 Interpretation of the high-impedance value (‘Z’)
331	16.8.3 The STD_MATCH function and predefined matching relational operators 16.8.4 Signal edge detection 16.8.5 Packages for arithmetic using bit and standard logic values 16.8.5.1 General
332	16.8.5.2 Allowable modifications
333	16.8.5.3 Compatibility with previous editions of IEEE Std 1076 16.9 Standard synthesis context declarations
334	16.10 Fixed-point package 16.11 Floating-point package
335	16.12 Reflection package 16.12.1 General
336	16.12.2 Package declaration
341	16.12.3 Package description 16.12.3.1 General
342	16.12.3.2 Common subtype and value mirrors
344	16.12.3.3 Enumeration subtype and value mirrors
345	16.12.3.4 Integer subtype and value mirrors
346	16.12.3.5 Floating subtype and value mirrors
347	16.12.3.6 Physical subtype and value mirrors
348	16.12.3.7 Record subtype and value mirrors
349	16.12.3.8 Array subtype and value mirrors
351	16.12.3.9 Access subtype and value mirrors
352	16.12.3.10 File subtype and value mirrors 16.12.3.11 Protected type and value mirrors
353	16.12.4 Examples 16.12.4.1 General 16.12.4.2 Length of discrete types
354	16.12.4.3 Generic to_string
356	17. VHDL Procedural Interface overview 17.1 General 17.2 Organization of the interface 17.2.1 General
357	17.2.2 VHPI naming conventions 17.3 Capability sets
359	17.4 Handles 17.4.1 General 17.4.2 Handle creation 17.4.3 Handle release
360	17.4.4 Handle comparison 17.4.5 Validity of handles
361	18. VHPI access functions 18.1 General 18.2 Information access functions 18.2.1 General 18.2.2 One-to-one association traversal
363	18.2.3 One-to-many association traversal 18.3 Property access functions 18.3.1 General 18.3.2 Integer and Boolean property access function
364	18.3.3 String property access function 18.3.4 Real property access function 18.3.5 Physical property access function 18.4 Access by name function
365	19. VHPI information model 19.1 General 19.2 Formal notation 19.2.1 General 19.2.2 Machine-readable information model
366	19.3 Class inheritance hierarchy
367	19.4 Name properties 19.4.1 General 19.4.2 Implicit labels of statements 19.4.2.1 General 19.4.2.2 Implicit labels of loop statements
368	19.4.2.3 Implicit labels of concurrent statements 19.4.3 The Name and CaseName properties
373	19.4.4 The SignatureName property 19.4.5 The UnitName property 19.4.6 The DefName and DefCaseName properties
377	19.4.7 The FullName and FullCaseName properties
380	19.4.8 The PathName and InstanceName properties 19.5 The stdUninstantiated package
383	19.6 The stdHierarchy package
389	19.7 The stdTypes package
392	19.8 The stdExpr package
395	19.9 The stdSpec package
397	19.10 The stdSubprograms package
399	19.11 The stdStmts package
405	19.12 The stdConnectivity package 19.12.1 Class diagrams
408	19.12.2 Contributors, loads, and simulated nets 19.12.2.1 General
409	19.12.2.2 Local contributors 19.12.2.3 Local loads
410	19.12.2.4 Simulated nets 19.13 The stdCallbacks package 19.14 The stdEngine package
411	19.15 The stdForeign package 19.16 The stdMeta package
413	19.17 The stdTool package
414	19.18 Application contexts
415	20. VHPI tool execution 20.1 General 20.2 Registration phase 20.2.1 General
416	20.2.2 Registration using a tabular registry
418	20.2.3 Registration using registration functions
419	20.2.4 Foreign attribute for foreign models 20.2.4.1 General 20.2.4.2 Standard indirect binding
420	20.2.4.3 Standard direct binding
421	20.3 Analysis phase 20.4 Elaboration phase 20.4.1 General
422	20.4.2 Dynamic elaboration
423	20.5 Initialization phase 20.6 Simulation phase 20.7 Save phase
424	20.8 Restart phase 20.9 Reset phase
425	20.10 Termination phase
426	21. VHPI callbacks 21.1 General 21.2 Callback functions 21.2.1 General 21.2.2 Registering callbacks
427	21.2.3 Enabling and disabling callbacks 21.2.4 Removing callbacks 21.2.5 Callback information 21.2.6 Execution of callbacks
428	21.3 Callback reasons 21.3.1 General 21.3.2 Object callbacks 21.3.2.1 General
429	21.3.2.2 vhpiCbValueChange 21.3.2.3 vhpiCbForce
430	21.3.2.4 vhpiCbRelease 21.3.2.5 vhpiCbTransaction 21.3.3 Foreign model callbacks 21.3.3.1 General 21.3.3.2 vhpiCbTimeOut and vhpiCbRepTimeOut
431	21.3.3.3 vhpiCbSensitivity
432	21.3.4 Statement callbacks 21.3.4.1 General 21.3.4.2 vhpiCbStmt
433	21.3.4.3 vhpiCbResume 21.3.4.4 vhpiCbSuspend
434	21.3.4.5 vhpiCbStartOfSubpCall 21.3.4.6 vhpiCbEndOfSubpCall 21.3.5 Time callbacks 21.3.5.1 General 21.3.5.2 vhpiCbAfterDelay and vhpiCbRepAfterDelay
435	21.3.6 Simulation phase callbacks 21.3.6.1 General 21.3.6.2 vhpiCbNextTimeStep and vhpiCbRepNextTimeStep 21.3.6.3 vhpiCbStartOfNextCycle and vhpiCbRepStartOfNextCycle 21.3.6.4 vhpiCbStartOfProcesses and vhpiCbRepStartOfProcesses 21.3.6.5 vhpiCbEndOfProcesses and vhpiCbRepEndOfProcesses 21.3.6.6 vhpiCbLastKnownDeltaCycle and vhpiCbRepLastKnownDeltaCycle 21.3.6.7 vhpiCbStartOfPostponed and vhpiCbRepStartOfPostponed
436	21.3.6.8 vhpiCbEndOfTimeStep and vhpiCbRepEndOfTimeStep 21.3.7 Action callbacks 21.3.7.1 General 21.3.7.2 vhpiCbStartOfTool and vhpiCbEndOfTool 21.3.7.3 vhpiCbStartOfAnalysis and vhpiCbEndOfAnalysis 21.3.7.4 vhpiCbStartOfElaboration and vhpiCbEndOfElaboration
437	21.3.7.5 vhpiCbStartOfInitialization and vhpiCbEndOfInitialization 21.3.7.6 vhpiCbStartOfSimulation and vhpiCbEndOfSimulation 21.3.7.7 vhpiCbQuiescense 21.3.7.8 vhpiCbEnterInteractive 21.3.7.9 vhpiCbExitInteractive
438	21.3.7.10 vhpiCbSigInterrupt 21.3.8 Save, restart, and reset callbacks 21.3.8.1 General 21.3.8.2 vhpiCbStartOfSave and vhpiCbEndOfSave 21.3.8.3 vhpiCbStartOfRestart and vhpiCbEndOfRestart
439	21.3.8.4 vhpiCbStartOfReset and vhpiCbEndOfReset
440	22. VHPI value access and update 22.1 General 22.2 Value structures and types 22.2.1 General 22.2.2 vhpiEnumT and vhpiSmallEnumT 22.2.3 vhpiIntT and vhpiLongIntT 22.2.4 vhpiCharT 22.2.5 vhpiRealT 22.2.6 vhpiPhysT and vhpiSmallPhysT
441	22.2.7 vhpiTimeT 22.2.8 vhpiValueT
443	22.3 Reading object values
444	22.4 Formatting values
446	22.5 Updating object values 22.5.1 General
447	22.5.2 updating an object of class variable 22.5.3 updating an object of class signal
449	22.5.4 Updating an object of class driver
450	22.5.5 Updating an object of class funcCall 22.6 Scheduling transactions on drivers
453	23. VHPI function reference 23.1 General 23.2 vhpi_assert
454	23.3 vhpi_check_error
457	23.4 vhpi_compare_handles
458	23.5 vhpi_control
460	23.6 vhpi_create
463	23.7 vhpi_disable_cb 23.8 vhpi_enable_cb
465	23.9 vhpi_format_value
466	23.10 vhpi_get
467	23.11 vhpi_get_cb_info
468	23.12 vhpi_get_data
470	23.13 vhpi_get_foreignf_info
471	23.14 vhpi_get_next_time
473	23.15 vhpi_get_phys 23.16 vhpi_get_real
474	23.17 vhpi_get_str
475	23.18 vhpi_get_time
476	23.19 vhpi_get_value
477	23.20 vhpi_handle
478	23.21 vhpi_handle_by_index
482	23.22 vhpi_handle_by_name
484	23.23 vhpi_is_printable
485	23.24 vhpi_iterator
486	23.25 vhpi_printf
487	23.26 vhpi_protected_call
491	23.27 vhpi_put_data
493	23.28 vhpi_put_value
494	23.29 vhpi_register_cb
497	23.30 vhpi_register_foreignf
500	23.31 vhpi_release_handle 23.32 vhpi_remove_cb
501	23.33 vhpi_scan
502	23.34 vhpi_schedule_transaction
507	23.35 vhpi_vprintf
508	24. Standard tool directives 24.1 Protect tool directives 24.1.1 General
510	24.1.2 Protect directives 24.1.2.1 Protect begin directive 24.1.2.2 Protect end directive 24.1.2.3 Protect begin protected directive 24.1.2.4 Protect end protected directive 24.1.2.5 Protect author directive 24.1.2.6 Protect author info directive
511	24.1.2.7 Protect encrypt agent directive 24.1.2.8 Protect encrypt agent info directive 24.1.2.9 Protect key keyowner directive 24.1.2.10 Protect key keyname directive 24.1.2.11 Protect key method directive 24.1.2.12 Protect key block directive
512	24.1.2.13 Protect data keyowner directive 24.1.2.14 Protect data keyname directive 24.1.2.15 Protect data method directive 24.1.2.16 Protect data block directive 24.1.2.17 Protect digest keyowner directive 24.1.2.18 Protect digest keyname directive 24.1.2.19 Protect digest key method directive
513	24.1.2.20 Protect digest method directive 24.1.2.21 Protect digest block directive 24.1.2.22 Protect encoding directive
514	24.1.2.23 Protect viewport directive 24.1.2.24 Protect license directives
515	24.1.2.25 Protect comment directive 24.1.2.26 Protect version directive 24.1.2.27 Protect key public key directive 24.1.3 Encoding, encryption, and digest methods 24.1.3.1 Encoding methods
516	24.1.3.2 Encryption methods
517	24.1.3.3 Digest methods
518	24.1.4 Encryption envelopes 24.1.4.1 General
519	24.1.4.2 Encrypt key specifications 24.1.4.3 Encrypt data specifications
520	24.1.4.4 Encrypt digest specifications 24.1.5 Decryption envelopes 24.1.5.1 General
521	24.1.5.2 Decrypt key blocks
522	24.1.5.3 Decrypt data blocks 24.1.5.4 Decrypt digest blocks
523	24.1.6 Protection requirements for decryption tools 24.1.7 Key management
524	24.1.8 Rights management 24.1.9 License management 24.1.10 Visibility management 24.1.11 Common rights 24.2 Conditional analysis tool directives 24.2.1 General
525	24.2.2 Standard conditional analysis identifiers
526	Annex A (informative) VHPI definitions file A.1 General A.2 VHPICharCodes
527	A.3 VHPI_GET_PRINTABLE_STRINGCODE
528	Annex B (normative) VHPI header file B.1 General B.2 Macros for sensitivity-set bitmaps B.2.1 General B.2.2 VHPI_SENS_ZERO B.2.3 VHPI_SENS_SET
529	B.2.4 VHPI_SENS_CLR B.2.5 VHPI_SENS_ISSET B.2.6 VHPI_SENS_FIRST
530	B.3 Implementation-specific extensions
531	Annex C (informative) Syntax summary
558	Annex D (informative) Potentially non-portable constructs
559	Annex E (informative) Changes from IEEE Std 1076-2008
560	Annex F (informative) Features under consideration for removal
561	Annex G (informative) Guide to use of standard packages G.1 Using the MATH_REAL and MATH_COMPLEX packages G.1.1 General G.1.2 Package bodies for MATH_REAL and MATH_COMPLEX G.1.3 Predefined data types, operators, and precision for MATH_REAL G.1.4 Use and constraints of pseudo-random number generator in MATH_REAL G.1.5 Precision across different platforms G.1.6 Handling of overflow/underflow conditions
562	G.1.7 Testbench for the packages G.1.8 Overloading side effect G.1.9 Synthesizability of functions G.2 Using the STD_LOGIC_1164 package G.2.1 General G.2.2 Value system
563	G.2.3 Handling strengths G.2.4 Use of the uninitialized value G.2.5 Behavioral modeling for ‘U’ propagation G.2.6 ‘U’s related to conditional expressions G.2.7 Structural modeling with logical tables G.2.8 X-handling: assignment of X’s
564	G.2.9 Modeling with don’t care’s G.2.9.1 Use of the don’t care state in synthesis models G.2.9.2 Semantics of ‘-‘ G.2.10 Resolution function G.2.11 Using STD_ULOGIC vs. STD_LOGIC
565	G.3 Notes on the synthesis package functions G.3.1 General G.3.2 General considerations G.3.2.1 Mixing SIGNED and UNSIGNED operands
566	G.3.2.2 Mixing vector and element operands G.3.3 Arithmetic operator functions G.3.3.1 Overflow of maximum negative value
567	G.3.3.2 Lack of carry and borrow
568	G.3.3.3 Return value for metalogical and high-impedance operands G.3.4 Relational operator functions G.3.4.1 Justification of vector operands G.3.4.2 Expansion of vector operands compared to integers G.3.4.3 Return value for metalogical and high-impedance operands
569	G.3.5 Shift functions G.3.5.1 Multiplication by a power of 2 with remainder G.3.5.2 Division by a power of 2 G.3.6 Type conversion functions G.3.6.1 Overflow in conversion to INTEGER G.3.6.2 Conversion between SIGNED and UNSIGNED
570	G.3.7 Logical operator functions G.3.7.1 Application to SIGNED and UNSIGNED G.3.7.2 Index range of return values G.3.8 The STD_MATCH function G.4 Using the fixed-point package G.4.1 General
571	G.4.2 Literals and type conversions
572	G.4.3 Sizing rules
574	G.4.4 Rounding and saturation G.4.5 Overloading
576	G.4.6 Package generics
578	G.4.7 Issues G.4.8 Catalog of operations G.4.8.1 Operators
580	G.4.8.2 Functions
581	G.4.8.3 Conversion functions
583	G.4.8.4 Sizing functions
584	G.4.8.5 Textio functions
585	G.5 Using the floating-point package G.5.1 Floating-point numbers
587	G.5.2 Use model
590	G.5.3 Package generics
592	G.5.4 Catalog of operations G.5.4.1 Operators
593	G.5.4.2 Functions
594	G.5.4.3 Conversion functions
595	G.5.4.4 IEEE 754 recommended functions and predicates
596	G.5.4.5 Functions returning constants G.5.4.6 Textio functions
598	Annex H (informative) Guide to use of protect directives H.1 General H.2 Simple protection envelopes H.2.1 Symmetric cipher and secret key
599	H.2.2 Default cipher and key
600	H.2.3 Specification of encoding method H.3 Digital envelopes H.3.1 Encryption for a single user
601	H.3.2 Encryption for multiple users
603	H.4 Digital signatures
604	H.5 Key exchange
606	Annex I (informative) Glossary
633	Annex J (informative) Bibliography
634	Index A
636	B
638	C
640	D
643	E
645	F
648	G
649	H-I
651	J
652	K-L
653	M
654	N
655	O
656	P
660	Q-R
662	S
666	T
668	U
669	V
672	W-Z
673	Back cover

Published By	Publication Date	Number of Pages
IEEE	2019	673


PDF Format	Searchable	Printable	Preview Now

Standard Title	IEEE Standard for VHDL Language Reference Manual
Published Code	IEEE
Publication Date	2019
Pages Count	673

IEEE 1076 2019

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