{"id":421071,"date":"2024-10-20T06:34:17","date_gmt":"2024-10-20T06:34:17","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/bs-en-61188-72017-2\/"},"modified":"2024-10-26T12:18:04","modified_gmt":"2024-10-26T12:18:04","slug":"bs-en-61188-72017-2","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/bsi\/bs-en-61188-72017-2\/","title":{"rendered":"BS EN 61188-7:2017"},"content":{"rendered":"
This part of IEC 61188 establishes a consistent technique for the description of electronic component orientation, and their land pattern geometries. This facilitates and encourages a common data capture and transfer methodology amongst and between global trading partners.<\/p>\n
PDF Pages<\/th>\n | PDF Title<\/th>\n<\/tr>\n | ||||||
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2<\/td>\n | undefined <\/td>\n<\/tr>\n | ||||||
7<\/td>\n | CONTENTS <\/td>\n<\/tr>\n | ||||||
8<\/td>\n | FOREWORD <\/td>\n<\/tr>\n | ||||||
10<\/td>\n | INTRODUCTION <\/td>\n<\/tr>\n | ||||||
11<\/td>\n | 1 Scope 2 Normative references 3 Terms and definitions 4 Basic rules 4.1 Common rules 4.2 General basic rules <\/td>\n<\/tr>\n | ||||||
12<\/td>\n | 4.3 Level A basic rule 4.4 Level B basic rule 4.5 File description definition <\/td>\n<\/tr>\n | ||||||
13<\/td>\n | 4.6 Component orientations Figures Figure 1 \u2013 Example of level A orientation concepts <\/td>\n<\/tr>\n | ||||||
14<\/td>\n | Tables Table 1 \u2013 Discrete component land pattern conventions <\/td>\n<\/tr>\n | ||||||
15<\/td>\n | Table 2 \u2013 Diode and transistor land pattern conventions <\/td>\n<\/tr>\n | ||||||
16<\/td>\n | Table 3 \u2013 Transistor and IC land pattern conventions <\/td>\n<\/tr>\n | ||||||
17<\/td>\n | Table 4 \u2013 Integrated circuit packages land pattern conventions <\/td>\n<\/tr>\n | ||||||
19<\/td>\n | Table 5 \u2013 Integrated circuit packages land pattern conventions <\/td>\n<\/tr>\n | ||||||
20<\/td>\n | Table 6 \u2013 BGA land pattern conventions <\/td>\n<\/tr>\n | ||||||
21<\/td>\n | Table 7 \u2013 Resistor array and connector land pattern conventions <\/td>\n<\/tr>\n | ||||||
22<\/td>\n | Table 8 \u2013 Level A land pattern convention summary <\/td>\n<\/tr>\n | ||||||
23<\/td>\n | 5 Origin point of land pattern 5.1 General 5.2 Surface mount components Table 9 \u2013 Level B land pattern convention summary <\/td>\n<\/tr>\n | ||||||
24<\/td>\n | 5.3 Through-hole leaded components 6 Land pattern to footprint comparison Figure 2 \u2013 Connector and switch library symbol examples Figure 3 \u2013 Through-hole components with terminal point of origin orientation <\/td>\n<\/tr>\n | ||||||
25<\/td>\n | 7 Components with one terminal 7.1 Surface mount components 7.2 Through-hole leaded components Figure 4 \u2013 Circular or square one-terminal component Figure 5 \u2013 Rectangular or oval one-terminal component Figure 6 \u2013 Surface mount components with one lead offset <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":" Printed boards and printed board assemblies. Design and use – Electronic component zero orientation for CAD library construction<\/b><\/p>\n |