{"id":248339,"date":"2024-10-19T16:21:34","date_gmt":"2024-10-19T16:21:34","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/bs-en-iec-62148-192019\/"},"modified":"2024-10-25T11:30:59","modified_gmt":"2024-10-25T11:30:59","slug":"bs-en-iec-62148-192019","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/bsi\/bs-en-iec-62148-192019\/","title":{"rendered":"BS EN IEC 62148-19:2019"},"content":{"rendered":"
This part of IEC 62148 covers the photonic chip scale package.<\/p>\n
The purpose of this document is to specify adequately the physical requirements of optical transmitters and receivers that will enable mechanical interchangeability of transmitters and receivers.<\/p>\n
PDF Pages<\/th>\n | PDF Title<\/th>\n<\/tr>\n | ||||||
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2<\/td>\n | National foreword <\/td>\n<\/tr>\n | ||||||
5<\/td>\n | Annex ZA(normative)Normative references to international publicationswith their corresponding European publications <\/td>\n<\/tr>\n | ||||||
7<\/td>\n | English CONTENTS <\/td>\n<\/tr>\n | ||||||
9<\/td>\n | FOREWORD <\/td>\n<\/tr>\n | ||||||
11<\/td>\n | INTRODUCTION <\/td>\n<\/tr>\n | ||||||
12<\/td>\n | 1 Scope 2 Normative references 3 Terms, definitions and abbreviated terms 3.1 Terms and definitions 3.2 Abbreviated terms <\/td>\n<\/tr>\n | ||||||
13<\/td>\n | 4 Classification 5 Specification of photonic chip scale package 5.1 General 5.2 General block diagram (silicon photonics) Figures Figure 1 \u2013 General block diagram for photonic chip scale package <\/td>\n<\/tr>\n | ||||||
14<\/td>\n | 5.3 Electrical interface 5.3.1 General 5.3.2 Numbering of electrical terminals 5.4 Optical interface 5.4.1 General 5.4.2 Free space optical beam condition 5.5 Outline and footprint 5.5.1 General Figure 2 \u2013 Electrical terminal numbering assignment (top view) <\/td>\n<\/tr>\n | ||||||
15<\/td>\n | 5.5.2 Drawing of footprint Figure 3 \u2013 Recommended pattern layout for PCB Figure 4 \u2013 Informative electrical strip line wiring for high speed electrical interface Tables Table 1 \u2013 Dimensions of recommended pattern layout for PCB <\/td>\n<\/tr>\n | ||||||
16<\/td>\n | Annex A (normative) Specific configurations A.1 General A.2 4ch transceiver A.2.1 Block diagram Table A.1 \u2013 Specific configurations specified in Annex A <\/td>\n<\/tr>\n | ||||||
17<\/td>\n | A.2.2 Electrical terminal assignments Figure A.1 \u2013 Block diagram for chip scale package of 4ch transceiver using silicon photonics chip with optional pads for LD control <\/td>\n<\/tr>\n | ||||||
18<\/td>\n | Figure A.2 \u2013 Electrical terminal numbering assignment (top view) Table A.2 \u2013 Terminal function definitions for a 4ch transceiver <\/td>\n<\/tr>\n | ||||||
20<\/td>\n | A.2.3 Optical terminal assignments <\/td>\n<\/tr>\n | ||||||
21<\/td>\n | A.2.4 Outline drawing Figure A.3 \u2013 Optical terminal numbering assignment for 0,25\u00a0mm pitch optical interface for 4ch transceiver (top view) Table A.3 \u2013 Optical terminal function definitions for 4ch transceiver <\/td>\n<\/tr>\n | ||||||
22<\/td>\n | Figure A.4 \u2013 Package outline drawing of 4ch transceiver Table A.4 \u2013 Dimensions of the package outline of 4ch transceiver <\/td>\n<\/tr>\n | ||||||
23<\/td>\n | A.3 8ch transceiver A.3.1 Block diagram <\/td>\n<\/tr>\n | ||||||
24<\/td>\n | A.3.2 Electrical terminal assignments Figure A.5 \u2013 Block diagram for chip scale package of 8ch transceiver using silicon photonics chip with optional pads for LD control <\/td>\n<\/tr>\n | ||||||
25<\/td>\n | Figure A.6 \u2013 Electrical terminal numbering assignment (top view) Table A.5 \u2013 Terminal function definitions for 8ch transceiver <\/td>\n<\/tr>\n | ||||||
28<\/td>\n | A.3.3 Optical terminal assignments Figure A.7 \u2013 Optical terminal numbering assignment for 0,125\u00a0mm pitch optical interface for 8ch transceiver (top view) <\/td>\n<\/tr>\n | ||||||
29<\/td>\n | A.3.4 Outline drawing Figure A.8 \u2013 Package outline drawing of 8ch transceiver Table A.6 \u2013 Optical terminal function definitions for 8ch transceiver <\/td>\n<\/tr>\n | ||||||
30<\/td>\n | A.4 12ch transmitter and receiver A.4.1 Block diagram Table A.7 \u2013 Dimensions of the package outline of 8ch transceiver <\/td>\n<\/tr>\n | ||||||
31<\/td>\n | Figure A.9 \u2013 Block diagram for chip scale package of 12ch transmitter using silicon photonics chip with optional pads for LD control Figure A.10 \u2013 Block diagram for the chip scale package of 12ch receiver with optional pad for PD bias <\/td>\n<\/tr>\n | ||||||
32<\/td>\n | A.4.2 Electrical terminal assignments Figure A.11 \u2013 Electrical terminal numbering assignment (top view) Table A.8 \u2013 Terminal function definitions for 12ch transmitter <\/td>\n<\/tr>\n | ||||||
35<\/td>\n | Table A.9 \u2013 Terminal function definitions for 12ch receiver <\/td>\n<\/tr>\n | ||||||
37<\/td>\n | A.4.3 Optical terminal assignments <\/td>\n<\/tr>\n | ||||||
38<\/td>\n | Figure A.12 \u2013 Optical terminal numbering assignment for 0,125\u00a0mm pitch optical interface for 12ch transmitter and receiver (top view) Table A.10 \u2013 Optical terminal function definitions for 12ch transmitter <\/td>\n<\/tr>\n | ||||||
39<\/td>\n | A.4.4 Outline drawing Figure A.13 \u2013 Package outline drawing of 12ch transmitter Table A.11 \u2013 Optical terminal function definitions for 12ch receiver <\/td>\n<\/tr>\n | ||||||
40<\/td>\n | Table A.12 \u2013 Dimensions of the package outline of 12ch transmitter <\/td>\n<\/tr>\n | ||||||
41<\/td>\n | Figure A.14 \u2013 Package outline drawing of 12ch receiver Table A.13 \u2013 Dimensions of the package outline of 12ch receiver <\/td>\n<\/tr>\n | ||||||
43<\/td>\n | Bibliography <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":" Fibre optic active components and devices. Package and interface standards – Photonic chip scale package<\/b><\/p>\n |