🔥🔥 Don’t Miss Out on Our End of Autumn Sale. If you have any questions, feel free to click the bottom right corner to contact our customer service..

Concat us[email protected]
Shopping Cart

No products in the cart.

🔍
BS ISO 17458-2:2013

BS ISO 17458-2:2013

$215.11

Road vehicles. FlexRay communications system – Data link layer specification

Published By Publication Date Number of Pages
BSI 2013 366
PDF Format Searchable Printable Preview Now
Guaranteed Safe Checkout
Categories: ,

If you have any questions, feel free to reach out to our online customer service team by clicking on the bottom right corner. We’re here to assist you 24/7.
Email:[email protected]

PDF Catalog

PDF Pages PDF Title
11 1 Scope
2 Normative references
3 Terms, definitions, symbols and abbreviated terms
3.1 Terms and definitions
17 3.2 Symbols
3.3 Abbreviated terms
20 4 Document overview
21 5 Conventions
5.1 General
5.2 Notational conventions
5.2.1 Parameter prefix conventions
22 5.2.2 Text coding
5.2.3 Implementation dependent behaviour
5.3 SDL conventions
5.3.1 General
23 5.3.2 SDL notational conventions
5.3.3 SDL extensions
5.3.3.1 General
5.3.3.2 Microtick, macrotick and sample tick timers
24 5.3.3.3 Microtick behaviour of the ‘now’ – expression
5.3.3.4 Channel-specific process replication
5.3.3.5 Handling of priority input symbols
25 5.3.3.6 Signals to non-instantiated processes
5.3.3.7 Exported and imported signals
5.4 Bit rates
5.5 Roles of a node in a FlexRay cluster
5.6 Synchronisation methods
5.6.1 General
26 5.6.2 TT-D synchronisation method
5.6.3 TT-L synchronisation method
27 5.6.4 TT-E synchronisation method
29 5.7 Network topology considerations
5.7.1 General
30 5.7.2 Passive bus topology
5.7.3 Active star topology
32 5.7.4 Active star topology combined with a passive bus top
34 5.8 Example node architecture
5.8.1 Objective
5.8.2 Overview
35 5.8.3 Host – communication controller interface
5.8.4 Communication controller – bus driver interface
37 5.8.5 Bus driver – host interface
5.8.5.1 Overview
5.8.5.2 Hard wired signals (option A)
5.8.5.3 Serial peripheral interface (SPI) (option B)
38 5.8.6 Bus driver – power supply interface (optional)
5.8.7 Time gateway interface
39 5.8.8 Testability requirements
6 Protocol operation control
6.1 Principles
6.1.1 General
40 6.1.2 Communication controller power moding
41 6.2 Description
6.2.1 Protocol operation control context
42 6.2.2 Operational overview
6.2.2.1 General
6.2.2.2 Host commands
44 6.2.2.3 Error conditions
6.2.2.3.1 General
6.2.2.3.2 Errors causing immediate entry to the POC:halt state
6.2.2.3.3 Errors handled by the degradation model
45 6.2.2.4 POC status
46 6.2.2.5 SDL considerations for single channel nodes
47 6.3 The protocol operation control process
6.3.1 General
6.3.2 POC SDL utilities
49 6.3.3 SDL organization
50 6.3.4 Preempting commands
51 6.3.5 Deferred commands
6.3.5.1 DEFERRED_HALT, DEFERRED_READY and CLEAR_DEFERRED commands
54 6.3.5.2 ALL_SLOTS command
6.3.6 Reaching the POC:ready state
6.3.6.1 State sequence to reach the POC:ready state
56 6.3.6.2 Default configuration requirements
57 6.3.7 Reaching the POC:normal active state
6.3.7.1 Host commands before reaching the POC:normal active state
58 6.3.7.2 Wakeup and startup support
60 6.3.8 Behaviour during normal operation
6.3.8.1 General
6.3.8.2 Cyclic behaviour
6.3.8.2.1 Recurring Tasks
61 6.3.8.2.2 Cycle counter
6.3.8.2.3 POC:normal active state
62 6.3.8.2.4 POC:normal passive state
64 6.3.8.2.5 Error checking during normal operation
6.3.8.2.5.1 Error checking overview
65 6.3.8.2.5.2 Error checking details for the POC:normal active state
67 6.3.8.2.5.3 Error checking details for the POC:normal passive state
69 7 Coding and Decoding
7.1 Principles
7.2 Description
70 7.2.1 Frame and symbol encoding
7.2.1.1 General
7.2.1.2 Frame encoding
7.2.1.2.1 Transmission start sequence
71 7.2.1.2.2 Frame start sequence
7.2.1.2.3 Byte start sequence
7.2.1.2.4 Frame end sequence
7.2.1.2.5 Dynamic trailing sequence
72 7.2.1.2.6 Frame bit stream assembly
73 7.2.1.3 Symbol encoding
7.2.1.3.1 General
7.2.1.3.2 Collision avoidance symbol and media access test symbol
74 7.2.1.3.3 Wakeup symbol
76 7.2.1.3.4 Wakeup During Operation Pattern (WUDOP)
77 7.2.2 Sampling and majority voting
78 7.2.3 Bit clock alignment and bit strobing
80 7.2.4 Implementation specific delays
7.2.5 Channel idle detection
7.2.6 Action point and time reference point
82 7.2.7 Frame and symbol decoding
7.2.7.1 Overview
83 7.2.7.2 Frame decoding
84 7.2.7.3 Symbol decoding
7.2.7.3.1 Collision avoidance symbol and media access test symbol decoding
85 7.2.7.3.2 Wakeup symbol decoding
86 7.2.7.4 Decoding error
7.2.8 Signal integrity
87 7.3 Coding and decoding process
7.3.1 Operating modes
7.3.2 Coding and decoding process behaviour
89 7.3.3 Encoding behaviour
92 7.3.4 Encoding macros
97 7.3.5 Decoding behaviour
98 7.3.6 Decoding macros
106 7.4 Bit strobing process
7.4.1 Operating modes
107 7.4.2 Bit strobing process behaviour
109 7.5 Wakeup pattern decoding process
7.5.1 Operating modes
110 7.5.2 Wakeup pattern decoding process behaviour
113 8 Frame Format
8.1 Overview
8.2 FlexRay header segment (5 bytes)
8.2.1 General
114 8.2.2 Reserved bit (1 bit)
8.2.3 Payload preamble indicator (1 bit)
8.2.4 Null frame indicator (1 bit)
115 8.2.5 Sync frame indicator (1 bit)
8.2.6 Startup frame indicator (1 bit)
116 8.2.7 Frame ID (11 bits)
8.2.8 Payload length (7 bits)
117 8.2.9 Header CRC (11 bits)
118 8.2.10 Cycle count (6 bits)
8.2.11 Formal header definition
8.3 FlexRay payload segment (0 – 254 bytes)
8.3.1 Payload
119 8.3.2 NMVector
120 8.3.3 Message ID (16 bits)
121 8.4 FlexRay trailer segment
8.5 CRC calculation details
8.5.1 Context of the CRC calculation
122 8.5.2 CRC calculation algorithm
8.5.3 Header CRC calculation
123 8.5.4 Frame CRC calculation
9 Media Access Control
9.1 Principles
9.1.1 Overview
9.1.2 Communication cycle
124 9.1.3 Communication cycle execution
126 9.1.4 Static segment
9.1.4.1 Structure of the static segment
9.1.4.2 Execution and timing of the static segment
127 9.1.5 Dynamic segment
9.1.5.1 Structure of the dynamic segment
128 9.1.5.2 Execution and timing of the dynamic segment
132 9.1.6 Symbol window
9.1.7 Network idle time
133 9.2 Description
9.2.1 Relationship to other processes
134 9.2.2 Operating modes
9.2.3 Significant events
9.2.3.1 Event types
9.2.3.2 Reception-related events
136 9.2.3.3 Transmission-related events
9.2.3.4 Timing-related events
9.3 Media access control process
9.3.1 States of the media access control process
138 9.3.2 Initialisation and MAC:standby state
139 9.3.3 Static segment related states
9.3.3.1 State machine for the static segment media access control
141 9.3.3.2 Transmission conditions and frame assembly in the static segment
144 9.3.4 Dynamic segment related states
9.3.4.1 State machine for the dynamic segment media access control
150 9.3.4.2 Transmission conditions and frame assembly in the dynamic segment
151 9.3.5 Symbol window related states
152 9.3.6 Network idle time
153 10 Frame and Symbol processing
10.1 Principles
10.2 Description
10.2.1 Relationship to other processes
154 10.2.2 Operating modes
155 10.2.3 Significant events
10.2.3.1 General
10.2.3.2 Reception-related events
156 10.2.3.3 Decoding-related events
10.2.3.4 Timing-related events
157 10.2.4 Status data
159 10.3 Frame and symbol processing process
10.3.1 States of the frame and symbol processing process
160 10.3.2 Initialisation and FSP:standby state
162 10.3.3 Macro SLOT_SEGMENT_END
163 10.3.4 FSP:wait for CE start state
164 10.3.5 FSP:decoding in progress state
10.3.5.1 Conditions to leave the FSP:decoding in progress state
166 10.3.5.2 Frame reception checks during non-synchronized operation
167 10.3.5.3 Frame reception checks during synchronized operation
10.3.5.3.1 Frame reception checks in the static segment
168 10.3.5.3.2 Frame reception checks in the dynamic segment
170 10.3.6 FSP:wait for CHIRP state
171 10.3.7 FSP:wait for transmission end state
11 Wakeup and Startup
11.1 General
172 11.2 Cluster wakeup
11.2.1 Principles
11.2.2 Description
173 11.2.3 Wakeup support by the communication controller
11.2.3.1 Host interaction
174 11.2.3.2 Wakeup state diagram
175 11.2.3.3 The POC:wakeup listen state
176 11.2.3.4 The POC:wakeup send state
177 11.2.3.5 The POC:wakeup detect state
11.3 Communication startup and reintegration
11.3.1 General
178 11.3.2 Principles
11.3.2.1 Definition and properties
11.3.2.2 Principle of operation
11.3.2.2.1 General
11.3.2.2.2 Startup performed by the coldstart nodes
179 11.3.2.2.3 Integration of the non-coldstart nodes
11.3.3 Description
180 11.3.4 Coldstart inhibit mode
11.3.5 Startup state diagram
11.3.5.1 Overview of the different startup paths
183 11.3.5.2 Path of a TT-D leading coldstart node
184 11.3.5.3 Path of a TT-D following coldstart node
11.3.5.4 Path of a TT-L coldstart node
185 11.3.5.5 Path of a TT-E coldstart node
188 11.3.5.6 Path of a non-coldstart node
189 11.3.5.7 The POC:coldstart listen state
191 11.3.5.8 The POC:coldstart collision resolution state
192 11.3.5.9 The POC:coldstart consistency check state
193 11.3.5.10 The POC:coldstart gap state
194 11.3.5.11 The POC:initialize schedule state
195 11.3.5.12 The POC:integration coldstart check state
196 11.3.5.13 The POC:coldstart join state
197 11.3.5.14 The POC:integration listen state
198 11.3.5.15 The POC:integration consistency check state
200 12 Clock synchronisation
12.1 Introduction
201 12.2 Time representation
12.2.1 Timing hierarchy
202 12.2.2 Global and local time
12.2.3 Parameters and variables
203 12.3 Synchronisation process
210 12.4 Startup of the clock synchronisation
12.4.1 Preconditions and startup types
212 12.4.2 Coldstart startup
12.4.3 Integration startup
214 12.5 Time measurement
12.5.1 General
12.5.2 Data structure
215 12.5.3 Initialisation
216 12.5.4 Time measurement storage
218 12.6 Correction term calculation
12.6.1 Fault-tolerant midpoint algorithm
219 12.6.2 Calculation of the offset correction value
221 12.6.3 Calculation of the rate correction value
223 12.6.4 Value limitations
224 12.6.5 Host-controlled external clock synchronisation
12.6.6 TT-E time gateway sink correction determination
230 12.7 Clock correction
233 12.8 Sync frame configuration
12.8.1 Configuration rules
234 12.8.2 TT-D cluster
12.8.3 TT-E cluster
235 12.8.4 TT-L cluster
12.9 Time gateway interface
236 13 Controller Host Interface
13.1 Principles
237 13.2 Description
238 13.3 Interfaces
13.3.1 Protocol data interface
13.3.1.1 Protocol configuration data
13.3.1.1.1 Host read and write access
13.3.1.1.2 Communication cycle timing configuration
239 13.3.1.1.3 Protocol operation configuration
240 13.3.1.1.4 Wakeup and startup configuration
241 13.3.1.1.5 Network Management Vector configuration
242 13.3.1.2 Protocol control data
13.3.1.2.1 Control of the protocol operation control
13.3.1.2.2 Control of MTS and WUDOP transmission
244 13.3.1.2.3 Control of external clock synchronisation
13.3.1.3 Protocol status data
13.3.1.3.1 Overview and general behaviour
13.3.1.3.2 Protocol operation control status
245 13.3.1.3.3 Wakeup and startup status
13.3.1.3.4 Communication cycle timing status
246 13.3.1.3.5 Synchronisation frame status
13.3.1.3.6 Startup frame status
247 13.3.1.3.7 Symbol window status
13.3.1.3.8 NIT status
248 13.3.1.3.9 Aggregated channel status
249 13.3.1.3.10 Dynamic segment status
13.3.2 Message data interface
13.3.2.1 Subject
13.3.2.2 Communication slot assignment
250 13.3.2.3 Communication slot assignment for transmission
13.3.2.3.1 General behaviour
13.3.2.3.2 Cycle-independent and cycle-dependent slot assignment
251 13.3.2.3.3 Transmission slot assignment list
13.3.2.3.4 Key slot assignment
13.3.2.4 Communication slot assignment for reception
252 13.3.2.5 Conflicting communication slot assignment for reception and transmission
13.3.2.6 Non-queued message buffers
13.3.2.6.1 Structure and general behaviour
13.3.2.6.2 Message buffer configuration data
254 13.3.2.6.3 Message buffer status data
13.3.2.6.4 Message buffer payload data and payload data valid flag
255 13.3.2.6.5 Buffer enabling and buffer locking
13.3.2.7 Non-queued message buffer identification
13.3.2.7.1 Principles of message buffer selection
256 13.3.2.7.2 Candidate transmit message buffer identification
257 13.3.2.7.3 Candidate receive message buffer identification
13.3.2.7.4 Selected transmit buffer identification
258 13.3.2.7.5 Selected receive buffer identification
13.3.2.7.6 Active message buffer identification
13.3.2.8 Message transmission
13.3.2.8.1 General concept
13.3.2.8.2 Transmit buffer configuration
260 13.3.2.8.3 Transmit buffer identification for message retrieval
13.3.2.8.4 Transmit buffer status
261 13.3.2.9 Message reception
13.3.2.9.1 Receive buffer types
262 13.3.2.9.2 Non-queued receive buffer configuration
263 13.3.2.9.3 Non-queued receive buffer contents
13.3.2.9.3.1 Slot status data
265 13.3.2.9.3.2 Frame contents data
266 13.3.2.10 Non-queued message buffer status update
267 13.3.2.11 General concept
13.3.2.11.1 The concept of queued receive buffers
13.3.2.11.2 Basic FIFO behaviour
13.3.2.11.2.1 Design of a FIFO buffer
269 13.3.2.11.2.2 Admittance into a FIFO
270 13.3.2.11.2.3 Reading and removal from a FIFO
13.3.2.11.3 FIFO admittance criteria
13.3.2.11.3.1 Overview
271 13.3.2.11.3.2 FIFO frame validity admittance criteria
13.3.2.11.3.3 FIFO channel admittance criteria
13.3.2.11.3.4 FIFO frame identifier admittance criteria
272 13.3.2.11.3.5 FIFO cycle counter admittance criteria
13.3.2.11.3.6 Message identifier admittance criteria
273 13.3.2.11.4 FIFO performance requirements
274 13.3.2.11.5 FIFO status information
275 13.3.3 CHI Services
13.3.3.1 Macrotick timer service
13.3.3.2 Interrupt service
276 13.3.3.3 Message ID filtering service
13.3.3.4 Network management service
363 Blank Page
364 Blank Page

Related products

BS ISO 17458-2:2013
$215.11