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BS EN 62386-102:2014:2015 Edition

BS EN 62386-102:2014:2015 Edition

$256.21

Digital addressable lighting interface – General requirements. Control gear

Published By Publication Date Number of Pages
BSI 2015 292
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IEC 62386-102:2014 is applicable to control gear in a bus system for control by digital signals of electronic lighting equipment. This electronic lighting equipment should be in line with the requirments of IEC 61347, with the addition of d.c. supplies. This second edition cancels and replaces the first edition published in 2009. This edition constitutes a technical revision. This edition includes the following significant technical changes with respect to the previous edition: a) elimination of all non-control gear relevant definitions, b) improvement of the requirements for control gear by clarifying the description, c) improvement of the test command iterations to increase the compatibility, d) addition of new commands, and e) the deletion of the requirements for: 1) timing; 2) control devices. The requirements for timing are now in Part 101 and the requirments for control devices are in Part 103. This publication is to be read in conjunction with /2

PDF Catalog

PDF Pages PDF Title
6 English
CONTENTS
16 INTRODUCTION
Figures
Figure 1 โ€“ IEC 62386 graphical overview
17 1 Scope
2 Normative references
3 Terms and definitions
20 4 General
4.1 General
4.2 Version number
5 Electrical specification
6 Interface power supply
21 7 Transmission protocol structure
7.1 General
7.2 16 bit forward frame encoding
8 Timing
Tables
Table 1 โ€“ 16-bit command frame encoding
22 9 Method of operation
9.1 General
9.2 Control gear
9.3 Dimming curve
Figure 2 โ€“ Control gear directly operating a light source
23 Figure 3 โ€“ Dimming curve
Table 2 โ€“ Dimming curve tolerance (%, rounded to two decimals)
24 Table 3 โ€“ Dimming curve
25 9.4 Calculating โ€œtargetLevelโ€
9.5 Fading
26 Figure 4 โ€“ Level over time, fading up and down
27 Table 4 โ€“ Fade times
28 Table 5 โ€“ Fade rates
29 Table 6 โ€“ Extended fade time – base value
Table 7 โ€“ Extended fade time – multiplier
31 9.6 Min and max level
9.7 Commands
33 9.8 Command iterations
Figure 5 โ€“ Timing and response when receiving a command iteration
34 9.9 Modes of operation
35 9.10 Memory banks
Table 8 โ€“ Basic memory map of memory banks
38 Table 9 โ€“ Memory map of memory bank 0
40 Table 10 โ€“ Memory map of memory bank 1
41 9.11 Reset
9.12 System failure
42 9.13 Power on
43 9.14 Assigning short addresses
Table 11 โ€“ Power on timing
45 9.15 Failure state behaviour
9.16 Status information
Table 12 โ€“ Control gear status
47 9.17 Non-volatile memory
9.18 Device types and features
48 9.19 Using scenes
Table 13 โ€“ Scenes
49 10 Declaration of variables
Table 14 โ€“ Declaration of variables
51 11 Definition of commands
11.1 General
11.2 Overview sheets
Table 15 โ€“ Standard commands
55 Table 16 โ€“ Special commands
57 11.3 Level instructions
60 11.4 Configuration instructions
65 11.5 Queries
67 Table 17 โ€“ Light source type encoding
69 11.6 Application extended commands
70 11.7 Special commands
Table 18 โ€“ Device addressing with โ€œINITIALISEโ€
74 12 Test procedures
12.1 General notes on test
76 Figure 6 โ€“ Fading from MIN LEVEL to MAX LEVEL
Figure 7 โ€“ Fading from MAX LEVEL to off
Figure 8 โ€“ Normal fading for a PWM dimmer
77 Figure 9 โ€“ Fading from MAX LEVEL to off for a PWM dimmer
78 Table 19 โ€“ Unexpected outcome
79 12.2 Preamble
84 Table 20 โ€“ Parameters for test sequence CheckFactoryDefault102
88 Table 21 โ€“ Parameters for test sequence CheckFactoryDefault201
89 Table 22 โ€“ Parameters for test sequence CheckFactoryDefault202
90 Table 23 โ€“ Parameters for test sequence CheckFactoryDefault203
Table 24 โ€“ Parameters for test sequence CheckFactoryDefault204
91 Table 25 โ€“ Parameters for test sequence CheckFactoryDefault205
Table 26 โ€“ Parameters for test sequence CheckFactoryDefault206
92 Table 27 โ€“ Parameters for test sequence CheckFactoryDefault207
Table 28 โ€“ Parameters for test sequence CheckFactoryDefault208
93 Table 29 โ€“ Parameters for test sequence CheckFactoryDefault209
96 12.3 Physical operational parameters
97 Table 30 โ€“ Parameters for test sequence Maximum and minimum system voltage
99 Figure 10 โ€“ Current rating test
101 Table 31 โ€“ Parameters for test sequence Transmitter voltages
102 Table 32 โ€“ Parameters for test sequence Transmitter rising and falling edges
103 Table 33 โ€“ Parameters for test sequence Transmitter rising and falling edges
104 Table 34 โ€“ Parameters for test sequence Transmitter bit timing
106 Table 35 โ€“ Parameters for test sequence Receiver frame timing
107 Table 36 โ€“ Parameters for test sequence Receiver start-up behavior
109 Table 37 โ€“ Parameters for test sequence Receiver bit timing
113 Table 38 โ€“ Parameters for test sequence Extended receiver bit timing
114 Table 39 โ€“ Parameters for test sequence Receiver frame violationand recovering after frame size violation
115 Table 40 โ€“ Parameters for test sequence Receiver frame timing
117 12.4 Configuration instructions
119 Table 41 โ€“ Parameters for test sequence RESET
124 Table 42 โ€“ Parameters for test sequence Send twice timeout
133 Table 43 โ€“ Parameters for test sequence Commands in-between
139 Table 44 โ€“ Parameters for test sequence SET MAX LEVEL
140 Table 45 โ€“ Parameters for test sequence SET MIN LEVEL
141 Table 46 โ€“ Parameters for test sequence SET SYSTEM FAILURE LEVEL
144 Table 47 โ€“ Parameters for test sequence SET POWER ON LEVEL
145 Table 48 โ€“ Parameters for test sequence SET FADE TIME
146 Table 49 โ€“ Parameters for test sequence SET FADE RATE
147 Table 50 โ€“ Parameters for test sequence SET SCENE / REMOVE FROM SCENE
148 Table 51 โ€“ Parameters for test sequence ADD TO GROUP / REMOVE FROM GROUP
149 Table 52 โ€“ Parameters for test sequence SET SHORT ADDRESS
150 Table 53 โ€“ Parameters for test sequence SET EXTENDED FADE TIME
153 Table 54 โ€“ Parameters for test sequence Reset/Power-on values
156 12.5 Memory banks
Table 55 โ€“ Parameters for test sequence DTR0 / DTR1 / DTR2
160 Table 56 โ€“ Parameters for test sequence READ MEMORY LOCATION on Memory Bank 0
163 Table 57 โ€“ Parameters for test sequence READ MEMORY LOCATION on Memory Bank 1
168 Table 58 โ€“ Parameters for test sequence Memory bank writing
171 Table 59 โ€“ Parameters for test sequence ENABLE WRITE MEMORY: writeEnableState
174 Table 60 โ€“ Parameters for test sequence ENABLE WRITE MEMORY: timeout / command in-between
176 Table 61 โ€“ Parameters for test sequence RESET MEMORY BANK:timeout / command in-between
178 12.6 Level instructions
Table 62 โ€“ Parameters for test sequence RESET MEMORY BANK
180 Table 63 โ€“ Parameters for test sequence Level instructions: Basic behaviour
183 Table 64 โ€“ Parameters for test sequence FADE TIME: possible values
186 Table 65 โ€“ Parameters for test sequence FADE TIME: transitions
188 Table 66 โ€“ Parameters for test sequence FADE TIME: fading to 0
191 Table 67 โ€“ Parameters for test sequence FADE TIME: small steps fading
192 Table 68 โ€“ Parameters for test sequence FADE TIME: extended fade time
195 Table 69 โ€“ Parameters for test sequence FADE RATE: possible values
196 Table 70 โ€“ Parameters for test sequence FADE RATE: possible values
197 Table 71 โ€“ Parameters for test sequence FADE RATE: transitions
198 Table 72 โ€“ Parameters for test sequence FADE RATE: extended fade time
201 Table 73 โ€“ Parameters for test sequence FADE TIME/FADE RATE: stop fading by setting MIN/MAX levels
205 Table 74 โ€“ Parameters for test sequence FADE TIME/FADE RATE: stop fading
207 Table 75 โ€“ Parameters for test sequence FADE TIME/FADE RATE: stop fading when a command is sent, check timing
212 Table 76 โ€“ Parameters for test sequence FADE TIME/FADE RATE: stop fading during startup
214 Table 77 โ€“ Parameters for test sequence Level instructions: combined instructions
219 Table 78 โ€“ Parameters for test sequence PowerOnLevel and SystemFailureLevel
221 Table 79 โ€“ Parameters for test sequence ENABLE DAPC SEQUENCE
222 Table 80 โ€“ Parameters for test sequence GO TO LAST ACTIVE LEVEL
224 Table 81 โ€“ Parameters for test sequence GO TO SCENE
226 Table 82 โ€“ Parameters for test sequence Power on: level control commands
227 Table 83 โ€“ Parameters for test sequence Logarithmic dimming curve
228 Table 84 โ€“ Parameters for test sequence Dimming curve: DAPC
231 Table 85 โ€“ Parameters for test sequence FADE TIME/EXTENDED FADE TIME: light output behaviour
234 12.7 Special commands
Table 86 โ€“ Parameters for test sequence Behaviour during a fade
237 Table 87 โ€“ Parameters for test sequence INITIALISE – device addressing
239 Table 88 โ€“ Parameters for test sequence COMPARE
240 Table 89 โ€“ Parameters for test sequence WITHDRAW
243 Table 90 โ€“ Parameters for test sequence PROGRAM SHORT ADDRESS
244 Table 91 โ€“ Parameters for test sequence VERIFY SHORT ADDRESS
245 Table 92 โ€“ Parameters for test sequence QUERY SHORT ADDRESS
248 Table 93 โ€“ Parameters for test sequence IDENTIFY DEVICE
252 12.8 Queries and reserved commands
Table 94 โ€“ Parameters for test sequence IDENTIFY DEVICE THROUGH RECALL MIN/MAX LEVEL
255 Table 95 โ€“ Parameters for test sequence QUERY STATUS – lampFailure/lampOn
256 Table 96 โ€“ Parameters for test sequence QUERY STATUS – lampOn
258 Table 97 โ€“ Parameters for test sequence QUERY STATUS – limitError/lampOn
260 Table 98 โ€“ Parameters for test sequence QUERY STATUS – powerCycleSeen
261 Table 99 โ€“ Parameters for test sequence QUERY CONTROL GEAR PRESENT
263 Table 100 โ€“ Parameters for test sequence Broadcast unaddressed
264 Table 101 โ€“ Parameters for test sequence Reserved commands: standard commands
265 Table 102 โ€“ Parameters for test sequence Reserved commands: special commands
268 12.9 Cross contamination
274 Table 103 โ€“ Parameters for test sequence Addressing 2
275 12.10 General subsequences
286 Annex A (informative) Examples of algorithms
A.1 Random address allocation
A.2 One single control gear connected to the control device
287 A.3 Using application extended commands
288 Annex B (normative) High resolution dimmer
289 Figure B.1 โ€“ Level behaviour in cases of off-grid starting points
290 Bibliography

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BS EN 62386-102:2014
$256.21