{"id":438547,"date":"2024-10-20T08:04:17","date_gmt":"2024-10-20T08:04:17","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/ieee-1685-2014\/"},"modified":"2024-10-26T15:08:19","modified_gmt":"2024-10-26T15:08:19","slug":"ieee-1685-2014","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/ieee\/ieee-1685-2014\/","title":{"rendered":"IEEE 1685-2014"},"content":{"rendered":"

Revision Standard – Superseded. Conformance checks for eXtensible Markup Language (XML) data designed to describe electronic systems are formulated by this standard. The meta-data forms that are standardized include components, systems, bus interfaces and connections, abstractions of those buses, and details of the components including address maps, register and field descriptions, and file set descriptions for use in automating design, verification, documentation, and use flows for electronic systems. A set of XML schemas of the form described by the World Wide Web Consortium (W3C(R)) and a set of semantic consistency rules (SCRs) are included. A generator interface that is portable across tool environments is provided. The specified combination of methodology-independent meta-data and the tool-independent mechanism for accessing that data provides for portability of design data, design methodologies, and environment implementations. (The PDF of this standard is available in the GETIEEE program. The “IEEE Get Program” grants public access to view and download individual PDFs of select standards at no charge. Visit https:\/\/ieeexplore.ieee.org\/browse\/standards\/get-program\/page for details.)<\/p>\n

PDF Catalog<\/h4>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
PDF Pages<\/th>\nPDF Title<\/th>\n<\/tr>\n
1<\/td>\nIEEE Std 1685-2014 Front Cover <\/td>\n<\/tr>\n
3<\/td>\nTitle page <\/td>\n<\/tr>\n
5<\/td>\nImportant Notices and Disclaimers Concerning IEEE Standards Documents <\/td>\n<\/tr>\n
8<\/td>\nParticipants <\/td>\n<\/tr>\n
9<\/td>\nIntroduction <\/td>\n<\/tr>\n
10<\/td>\nContents <\/td>\n<\/tr>\n
13<\/td>\nIMPORTANT NOTICE
\n
1. Overview
1.1 Scope <\/td>\n<\/tr>\n
14<\/td>\n1.2 Purpose
1.3 Design environment
1.3.1 IP-XACT design environment <\/td>\n<\/tr>\n
15<\/td>\n1.3.2 IP-XACT object descriptions
1.3.3 Object interactions <\/td>\n<\/tr>\n
16<\/td>\n1.3.4 IP-XACT generators
1.3.5 IP-XACT design environment interfaces <\/td>\n<\/tr>\n
17<\/td>\n1.3.6 Tight generator interface
1.3.7 Design intellectual property <\/td>\n<\/tr>\n
18<\/td>\n1.4 IP-XACT\u2013enabled implementations
1.4.1 Design environments <\/td>\n<\/tr>\n
19<\/td>\n1.4.2 Point tools
1.4.3 IPs
1.4.4 Generators
1.5 Conventions used
1.5.1 Visual cues (meta-syntax) <\/td>\n<\/tr>\n
20<\/td>\n1.5.2 Notational conventions
1.5.3 Syntax examples
1.5.4 Graphics used to document the schema <\/td>\n<\/tr>\n
24<\/td>\n1.6 Use of color in this standard
1.7 Contents of this standard <\/td>\n<\/tr>\n
25<\/td>\n2. Normative references <\/td>\n<\/tr>\n
27<\/td>\n3. Definitions, acronyms, and abbreviations
3.1 Definitions <\/td>\n<\/tr>\n
32<\/td>\n3.2 Acronyms and abbreviations <\/td>\n<\/tr>\n
33<\/td>\n4. Interoperability use model
4.1 Roles and responsibilities
4.1.1 Component IP provider
4.1.2 SoC design IP provider
4.1.3 SoC design IP consumer
4.1.4 Design tool supplier <\/td>\n<\/tr>\n
34<\/td>\n4.2 IP-XACT IP exchange flows
4.2.1 Component or SoC design IP provider use model <\/td>\n<\/tr>\n
35<\/td>\n4.2.2 Generator provider use model
4.2.3 System design tool provider use model <\/td>\n<\/tr>\n
37<\/td>\n5. Interface definition descriptions
5.1 Definition descriptions <\/td>\n<\/tr>\n
38<\/td>\n5.2 Bus definition
5.2.1 Schema
5.2.2 Description <\/td>\n<\/tr>\n
40<\/td>\n5.3 Abstraction definition
5.3.1 Schema
5.3.2 Description <\/td>\n<\/tr>\n
41<\/td>\n5.4 Ports
5.4.1 Schema
5.4.2 Description <\/td>\n<\/tr>\n
42<\/td>\n5.5 Wire ports
5.5.1 Schema
5.5.2 Description <\/td>\n<\/tr>\n
43<\/td>\n5.6 Qualifiers
5.6.1 Schema
5.6.2 Description <\/td>\n<\/tr>\n
44<\/td>\n5.7 Wire port group
5.7.1 Schema <\/td>\n<\/tr>\n
45<\/td>\n5.7.2 Description
5.8 Wire port mode (and mirrored mode) constraints
5.8.1 Schema <\/td>\n<\/tr>\n
46<\/td>\n5.8.2 Description
5.9 Transactional ports
5.9.1 Schema
5.9.2 Description <\/td>\n<\/tr>\n
48<\/td>\n5.10 Transactional port group
5.10.1 Schema
5.10.2 Description <\/td>\n<\/tr>\n
49<\/td>\n5.11 Extending bus and abstraction definitions
5.11.1 Extending bus definitions
5.11.2 Extending abstraction definitions <\/td>\n<\/tr>\n
50<\/td>\n5.11.3 Modifying definitions <\/td>\n<\/tr>\n
51<\/td>\n5.12 Clock and reset handling <\/td>\n<\/tr>\n
53<\/td>\n6. Component descriptions
6.1 Component
6.1.1 Schema
6.1.2 Description <\/td>\n<\/tr>\n
55<\/td>\n6.2 Interfaces
6.2.1 Direct interface modes <\/td>\n<\/tr>\n
56<\/td>\n6.2.2 Mirrored interface modes
6.2.3 Monitor interface modes
6.3 Interface interconnections
6.3.1 Direct connection
6.3.2 Mirrored-non-mirrored connection
6.3.3 Monitor connection <\/td>\n<\/tr>\n
57<\/td>\n6.3.4 Broadcast connections
6.3.5 Interface logical to physical port mapping <\/td>\n<\/tr>\n
58<\/td>\n6.4 Complex interface interconnections
6.4.1 Channel <\/td>\n<\/tr>\n
59<\/td>\n6.4.2 Bridge <\/td>\n<\/tr>\n
60<\/td>\n6.5 Bus interfaces
6.5.1 busInterface <\/td>\n<\/tr>\n
62<\/td>\n6.5.2 Interface modes <\/td>\n<\/tr>\n
64<\/td>\n6.5.3 Master interface <\/td>\n<\/tr>\n
65<\/td>\n6.5.4 Slave interface <\/td>\n<\/tr>\n
66<\/td>\n6.5.5 Mirrored slave interface <\/td>\n<\/tr>\n
67<\/td>\n6.5.6 Abstraction types <\/td>\n<\/tr>\n
68<\/td>\n6.5.7 Port map <\/td>\n<\/tr>\n
70<\/td>\n6.6 Indirect interfaces
6.6.1 Schema
6.6.2 Description <\/td>\n<\/tr>\n
71<\/td>\n6.7 Component channels
6.7.1 Schema <\/td>\n<\/tr>\n
72<\/td>\n6.7.2 Description
6.8 Address spaces <\/td>\n<\/tr>\n
73<\/td>\n6.8.1 addressSpaces <\/td>\n<\/tr>\n
74<\/td>\n6.8.2 Segments <\/td>\n<\/tr>\n
75<\/td>\n6.8.3 executableImage <\/td>\n<\/tr>\n
76<\/td>\n6.8.4 languageTools <\/td>\n<\/tr>\n
78<\/td>\n6.8.5 fileBuilder <\/td>\n<\/tr>\n
79<\/td>\n6.8.6 Local memory map <\/td>\n<\/tr>\n
80<\/td>\n6.9 Memory maps
6.9.1 memoryMaps <\/td>\n<\/tr>\n
81<\/td>\n6.9.2 Address block <\/td>\n<\/tr>\n
82<\/td>\n6.9.3 Address block definition group <\/td>\n<\/tr>\n
83<\/td>\n6.9.4 memoryBlockData group <\/td>\n<\/tr>\n
85<\/td>\n6.9.5 Bank <\/td>\n<\/tr>\n
87<\/td>\n6.9.6 Banked address block <\/td>\n<\/tr>\n
88<\/td>\n6.9.7 Banked bank <\/td>\n<\/tr>\n
89<\/td>\n6.9.8 Banked subspace <\/td>\n<\/tr>\n
90<\/td>\n6.9.9 Subspace map <\/td>\n<\/tr>\n
91<\/td>\n6.10 Remapping
6.10.1 Memory remap <\/td>\n<\/tr>\n
92<\/td>\n6.10.2 Remap states <\/td>\n<\/tr>\n
93<\/td>\n6.11 Registers
6.11.1 Register data <\/td>\n<\/tr>\n
94<\/td>\n6.11.2 Register <\/td>\n<\/tr>\n
95<\/td>\n6.11.3 Register definition group <\/td>\n<\/tr>\n
96<\/td>\n6.11.4 Alternate registers <\/td>\n<\/tr>\n
97<\/td>\n6.11.5 Alternate register definition group <\/td>\n<\/tr>\n
99<\/td>\n6.11.6 Register file <\/td>\n<\/tr>\n
100<\/td>\n6.11.7 Register file definition group <\/td>\n<\/tr>\n
101<\/td>\n6.11.8 Register bit fields <\/td>\n<\/tr>\n
103<\/td>\n6.11.9 Field data group <\/td>\n<\/tr>\n
105<\/td>\n6.11.10 Enumeration values <\/td>\n<\/tr>\n
106<\/td>\n6.11.11 Write value constraint <\/td>\n<\/tr>\n
107<\/td>\n6.12 Models
6.12.1 Model <\/td>\n<\/tr>\n
109<\/td>\n6.12.2 instantiationsGroup <\/td>\n<\/tr>\n
110<\/td>\n6.12.3 componentInstantiation <\/td>\n<\/tr>\n
112<\/td>\n6.12.4 designInstantiation <\/td>\n<\/tr>\n
113<\/td>\n6.12.5 designConfigurationInstantiation <\/td>\n<\/tr>\n
114<\/td>\n6.12.6 Module parameters <\/td>\n<\/tr>\n
117<\/td>\n6.12.7 Component ports <\/td>\n<\/tr>\n
118<\/td>\n6.12.8 Component wire ports <\/td>\n<\/tr>\n
120<\/td>\n6.12.9 Component wireTypeDef <\/td>\n<\/tr>\n
122<\/td>\n6.12.10 Component driver <\/td>\n<\/tr>\n
124<\/td>\n6.12.11 Component driver\/clockDriver <\/td>\n<\/tr>\n
125<\/td>\n6.12.12 Implementation constraints <\/td>\n<\/tr>\n
126<\/td>\n6.12.13 Component wire port constraints <\/td>\n<\/tr>\n
127<\/td>\n6.12.14 Port timing constraints <\/td>\n<\/tr>\n
128<\/td>\n6.12.15 Load and drive constraint cell specification <\/td>\n<\/tr>\n
129<\/td>\n6.12.16 Other clock drivers <\/td>\n<\/tr>\n
130<\/td>\n6.12.17 Component transactional port type <\/td>\n<\/tr>\n
131<\/td>\n6.12.18 Component transactional protocol\/payload definition <\/td>\n<\/tr>\n
132<\/td>\n6.12.19 Component transactional port type definition <\/td>\n<\/tr>\n
133<\/td>\n6.12.20 Component transactional port service
6.12.21 Phantom ports <\/td>\n<\/tr>\n
134<\/td>\n6.13 Component generators
6.13.1 Schema <\/td>\n<\/tr>\n
135<\/td>\n6.13.2 Description <\/td>\n<\/tr>\n
136<\/td>\n6.14 Choices
6.14.1 Schema
6.14.2 Description <\/td>\n<\/tr>\n
137<\/td>\n6.15 File sets
6.15.1 fileSets <\/td>\n<\/tr>\n
138<\/td>\n6.15.2 file <\/td>\n<\/tr>\n
140<\/td>\n6.15.3 buildCommand <\/td>\n<\/tr>\n
141<\/td>\n6.15.4 defaultFileBuilder <\/td>\n<\/tr>\n
142<\/td>\n6.15.5 function <\/td>\n<\/tr>\n
143<\/td>\n6.15.6 sourceFile
6.16 White box elements <\/td>\n<\/tr>\n
144<\/td>\n6.16.1 Schema
6.16.2 Description <\/td>\n<\/tr>\n
145<\/td>\n6.17 White box element reference
6.17.1 Schema
6.17.2 Description <\/td>\n<\/tr>\n
146<\/td>\n6.18 CPUs
6.18.1 Schema
6.18.2 Description <\/td>\n<\/tr>\n
147<\/td>\n6.19 Reset types
6.19.1 Schema
6.19.2 Description <\/td>\n<\/tr>\n
149<\/td>\n7. Design descriptions
7.1 Design
7.1.1 Schema
7.1.2 Description <\/td>\n<\/tr>\n
150<\/td>\n7.2 Design component instances
7.2.1 Schema
7.2.2 Description <\/td>\n<\/tr>\n
151<\/td>\n7.3 Design interconnections
7.3.1 interconnection <\/td>\n<\/tr>\n
152<\/td>\n7.3.2 monitorInterconnection <\/td>\n<\/tr>\n
153<\/td>\n7.4 Active, hierarchical, monitored, and monitor interfaces
7.4.1 Schema <\/td>\n<\/tr>\n
155<\/td>\n7.4.2 Description <\/td>\n<\/tr>\n
156<\/td>\n7.5 Design ad hoc connections
7.5.1 Schema
7.5.2 Description <\/td>\n<\/tr>\n
157<\/td>\n7.5.3 Ad hoc wire connection
7.5.4 Ad hoc transactional connection
7.5.5 Interaction rules between an interface-based connection and ad hoc connections <\/td>\n<\/tr>\n
158<\/td>\n7.6 Port references
7.6.1 Schema
7.6.2 Description <\/td>\n<\/tr>\n
161<\/td>\n8. Abstractor descriptions
8.1 Abstractor
8.1.1 Schema <\/td>\n<\/tr>\n
162<\/td>\n8.1.2 Description <\/td>\n<\/tr>\n
163<\/td>\n8.2 Abstractor interfaces
8.2.1 Schema
8.2.2 Description <\/td>\n<\/tr>\n
164<\/td>\n8.3 Abstractor models
8.3.1 Schema
8.3.2 Description
8.4 Abstractor views
8.4.1 Schema <\/td>\n<\/tr>\n
165<\/td>\n8.4.2 Description
8.5 Abstractor ports
8.5.1 Schema <\/td>\n<\/tr>\n
166<\/td>\n8.5.2 Description <\/td>\n<\/tr>\n
167<\/td>\n8.6 Abstractor wire ports
8.6.1 Schema
8.6.2 Description <\/td>\n<\/tr>\n
168<\/td>\n8.7 Abstractor generators
8.7.1 Schema <\/td>\n<\/tr>\n
169<\/td>\n8.7.2 Description <\/td>\n<\/tr>\n
171<\/td>\n9. Generator chain descriptions
9.1 generatorChain
9.1.1 Schema <\/td>\n<\/tr>\n
172<\/td>\n9.1.2 Description <\/td>\n<\/tr>\n
173<\/td>\n9.2 generatorChainSelector
9.2.1 Schema
9.2.2 Description <\/td>\n<\/tr>\n
174<\/td>\n9.3 generatorChain component selector
9.3.1 Schema
9.3.2 Description <\/td>\n<\/tr>\n
175<\/td>\n9.4 generatorChain generator
9.4.1 Schema
9.4.2 Description <\/td>\n<\/tr>\n
177<\/td>\n10. Design configuration descriptions
10.1 Design configuration <\/td>\n<\/tr>\n
178<\/td>\n10.2 designConfiguration
10.2.1 Schema
10.2.2 Description <\/td>\n<\/tr>\n
179<\/td>\n10.3 interconnectionConfiguration
10.3.1 Schema
10.3.2 Description <\/td>\n<\/tr>\n
180<\/td>\n10.4 abstractorInstance
10.4.1 Schema <\/td>\n<\/tr>\n
181<\/td>\n10.4.2 Description
10.5 viewConfiguration
10.5.1 Schema
10.5.2 Description <\/td>\n<\/tr>\n
183<\/td>\n11. Catalog descriptions
11.1 catalog
11.1.1 Schema <\/td>\n<\/tr>\n
184<\/td>\n11.1.2 Description <\/td>\n<\/tr>\n
185<\/td>\n11.2 ipxactFile
11.2.1 Schema
11.2.2 Description <\/td>\n<\/tr>\n
187<\/td>\n12. Addressing
12.1 Calculating the bit address of a bit in a memory map <\/td>\n<\/tr>\n
189<\/td>\n12.2 Calculating the bus address at the slave bus interface
12.3 Calculating the address at the indirect interface <\/td>\n<\/tr>\n
190<\/td>\n12.4 Address modifications of a channel
12.5 Addressing in the master
12.6 Address translation in a bridge <\/td>\n<\/tr>\n
192<\/td>\n13. Data visibility
13.1 Mapped address bits mask
13.2 Address modifications of an interconnection
13.3 Bit steering in a channel <\/td>\n<\/tr>\n
193<\/td>\n13.4 Visibility of bits
13.4.1 Visible address ranges
13.4.2 Bit lanes in memory maps <\/td>\n<\/tr>\n
194<\/td>\n13.4.3 Bit lanes in address spaces
13.4.4 Bit lanes in bus interfaces
13.4.5 Bit lanes in channels
13.4.6 Bit steering in masters and slaves <\/td>\n<\/tr>\n
197<\/td>\nAnnex A (informative) Bibliography <\/td>\n<\/tr>\n
199<\/td>\nAnnex B (normative) Semantic consistency rules <\/td>\n<\/tr>\n
229<\/td>\nAnnex C (normative) Common elements and concepts <\/td>\n<\/tr>\n
263<\/td>\nAnnex D (normative) Types <\/td>\n<\/tr>\n
265<\/td>\nAnnex E (normative) SystemVerilog expressions <\/td>\n<\/tr>\n
279<\/td>\nAnnex F (normative) Tight generator interface <\/td>\n<\/tr>\n
471<\/td>\nAnnex G (informative) External bus with an internal\/digital interface <\/td>\n<\/tr>\n
473<\/td>\nAnnex H (informative) Bridges and channels <\/td>\n<\/tr>\n
483<\/td>\nAnnex I (informative) Examples <\/td>\n<\/tr>\n
510<\/td>\nBack Cover <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":"

IEEE Standard for IP-XACT, Standard Structure for Packaging, Integrating, and Reusing IP within Tool Flows (Superseded)<\/b><\/p>\n\n\n\n\n
Published By<\/td>\nPublication Date<\/td>\nNumber of Pages<\/td>\n<\/tr>\n
IEEE<\/b><\/a><\/td>\n2014<\/td>\n<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n","protected":false},"featured_media":438555,"template":"","meta":{"rank_math_lock_modified_date":false,"ep_exclude_from_search":false},"product_cat":[2644],"product_tag":[],"class_list":{"0":"post-438547","1":"product","2":"type-product","3":"status-publish","4":"has-post-thumbnail","6":"product_cat-ieee","8":"first","9":"instock","10":"sold-individually","11":"shipping-taxable","12":"purchasable","13":"product-type-simple"},"_links":{"self":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product\/438547","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product"}],"about":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/types\/product"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media\/438555"}],"wp:attachment":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media?parent=438547"}],"wp:term":[{"taxonomy":"product_cat","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_cat?post=438547"},{"taxonomy":"product_tag","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_tag?post=438547"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}