{"id":420902,"date":"2024-10-20T06:33:27","date_gmt":"2024-10-20T06:33:27","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/bs-iec-630032015-2\/"},"modified":"2024-10-26T12:16:21","modified_gmt":"2024-10-26T12:16:21","slug":"bs-iec-630032015-2","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/bsi\/bs-iec-630032015-2\/","title":{"rendered":"BS IEC 63003:2015"},"content":{"rendered":"

The scope of this standard is the definition of a pin map utilizing the IEEE 1505\u2122 1<\/sup> receiver fixture interface (RFI). The pin map defined within this standard shall apply to military and aerospace automatic test equipment (ATE) testing applications.<\/p>\n

PDF Catalog<\/h4>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
PDF Pages<\/th>\nPDF Title<\/th>\n<\/tr>\n
4<\/td>\nCONTENTS <\/td>\n<\/tr>\n
11<\/td>\n1. Overview
1.1 Scope <\/td>\n<\/tr>\n
12<\/td>\n1.2 Purpose
1.3 Statement of the problem <\/td>\n<\/tr>\n
13<\/td>\n2. Normative references <\/td>\n<\/tr>\n
14<\/td>\n3. Definitions, acronyms, and abbreviations
3.1 Definitions
3.2 Specification terms
3.3 Acronyms and abbreviations <\/td>\n<\/tr>\n
18<\/td>\n4. Common test interface requirements
4.1 Introduction
4.2 CTI open system requirements <\/td>\n<\/tr>\n
19<\/td>\n4.3 CTI cost requirements
4.4 Vertical integration test support requirements <\/td>\n<\/tr>\n
20<\/td>\n4.5 CTI configuration\/interoperability requirements
4.6 Maintainability\/end-user support requirements
4.7 Scaleable architecture requirements <\/td>\n<\/tr>\n
22<\/td>\n4.8 Physical framework requirements <\/td>\n<\/tr>\n
27<\/td>\n4.9 Reliability requirements <\/td>\n<\/tr>\n
28<\/td>\n4.10 CTI connector footprint\/parametric requirements <\/td>\n<\/tr>\n
32<\/td>\n4.11 CTI pin map requirements <\/td>\n<\/tr>\n
43<\/td>\n4.12 CTI pin map input\/output configuration <\/td>\n<\/tr>\n
44<\/td>\nAnnex A (normative) Common test interface signal definitions for pin map <\/td>\n<\/tr>\n
169<\/td>\nAnnex B (informative) Bibliography <\/td>\n<\/tr>\n
171<\/td>\nAnnex C (informative) IEEE List of Participants <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":"

Standard for the common test interface pin map configuration for high-density, single-tier electronics test requirements utilizing IEEE Std 1505TM<\/sup><\/b><\/p>\n\n\n\n\n
Published By<\/td>\nPublication Date<\/td>\nNumber of Pages<\/td>\n<\/tr>\n
BSI<\/b><\/a><\/td>\n2016<\/td>\n174<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n","protected":false},"featured_media":420908,"template":"","meta":{"rank_math_lock_modified_date":false,"ep_exclude_from_search":false},"product_cat":[381,2641],"product_tag":[],"class_list":{"0":"post-420902","1":"product","2":"type-product","3":"status-publish","4":"has-post-thumbnail","6":"product_cat-25-040-01","7":"product_cat-bsi","9":"first","10":"instock","11":"sold-individually","12":"shipping-taxable","13":"purchasable","14":"product-type-simple"},"_links":{"self":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product\/420902","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product"}],"about":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/types\/product"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media\/420908"}],"wp:attachment":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media?parent=420902"}],"wp:term":[{"taxonomy":"product_cat","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_cat?post=420902"},{"taxonomy":"product_tag","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_tag?post=420902"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}