{"id":211709,"date":"2024-10-19T13:41:53","date_gmt":"2024-10-19T13:41:53","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/ieee-1801-2018\/"},"modified":"2024-10-25T06:30:29","modified_gmt":"2024-10-25T06:30:29","slug":"ieee-1801-2018","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/ieee\/ieee-1801-2018\/","title":{"rendered":"IEEE 1801 2018"},"content":{"rendered":"

Revision Standard – Active. A method is provided for specifying power intent for an electronic design, for use in verification of the structure and behavior of the design in the context of a given power management architecture, and for driving implementation of that power-management architecture. The method supports incremental refinement of power intent specifications required for IP-based design flows.(The PDF of this standard is available to you at no cost thru the IEEE GET program https:\/\/ieeexplore.ieee.org\/browse\/standards\/get-program\/page)<\/p>\n

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PDF Pages<\/th>\nPDF Title<\/th>\n<\/tr>\n
1<\/td>\nIEEE Std 1801\u2122-2018 Front cover <\/td>\n<\/tr>\n
2<\/td>\nTitle page <\/td>\n<\/tr>\n
4<\/td>\nImportant Notices and Disclaimers Concerning IEEE Standards Documents <\/td>\n<\/tr>\n
7<\/td>\nParticipants <\/td>\n<\/tr>\n
8<\/td>\nIntroduction <\/td>\n<\/tr>\n
10<\/td>\nContents <\/td>\n<\/tr>\n
14<\/td>\n1. Overview
1.1 Scope
1.2 Purpose
1.3 Key characteristics of the Unified Power Format <\/td>\n<\/tr>\n
16<\/td>\n1.4 Contents of this standard <\/td>\n<\/tr>\n
17<\/td>\n2. Normative references
3. Definitions, acronyms, and abbreviations
3.1 Definitions <\/td>\n<\/tr>\n
23<\/td>\n3.2 Acronyms and abbreviations <\/td>\n<\/tr>\n
24<\/td>\n4. Concepts
4.1 Introduction <\/td>\n<\/tr>\n
25<\/td>\n4.2 Design structure
4.3 Design representation <\/td>\n<\/tr>\n
29<\/td>\n4.4 Power architecture <\/td>\n<\/tr>\n
32<\/td>\n4.5 Power distribution <\/td>\n<\/tr>\n
40<\/td>\n4.6 Power management <\/td>\n<\/tr>\n
45<\/td>\n4.7 Supply states and power states <\/td>\n<\/tr>\n
52<\/td>\n4.8 Simstates <\/td>\n<\/tr>\n
53<\/td>\n4.9 Power intent specification <\/td>\n<\/tr>\n
59<\/td>\n5. Language basics
5.1 UPF is Tcl <\/td>\n<\/tr>\n
60<\/td>\n5.2 Conventions used <\/td>\n<\/tr>\n
62<\/td>\n5.3 Lexical elements <\/td>\n<\/tr>\n
66<\/td>\n5.4 Boolean expressions <\/td>\n<\/tr>\n
68<\/td>\n5.5 Object declaration
5.6 Attributes of objects <\/td>\n<\/tr>\n
73<\/td>\n5.7 Precedence <\/td>\n<\/tr>\n
76<\/td>\n5.8 Generic UPF command semantics <\/td>\n<\/tr>\n
77<\/td>\n5.9 effective_element_list semantics <\/td>\n<\/tr>\n
80<\/td>\n5.10 Command refinement <\/td>\n<\/tr>\n
81<\/td>\n5.11 Error handling
5.12 Units
5.13 SystemC language basic <\/td>\n<\/tr>\n
82<\/td>\n6. Power intent commands
6.1 Introduction
6.2 Categories <\/td>\n<\/tr>\n
83<\/td>\n6.3 add_parameter <\/td>\n<\/tr>\n
84<\/td>\n6.4 add_port_state (legacy) <\/td>\n<\/tr>\n
85<\/td>\n6.5 add_power_state <\/td>\n<\/tr>\n
92<\/td>\n6.6 add_pst_state (legacy) <\/td>\n<\/tr>\n
93<\/td>\n6.7 add_state_transition <\/td>\n<\/tr>\n
95<\/td>\n6.8 add_supply_state <\/td>\n<\/tr>\n
96<\/td>\n6.9 apply_power_model <\/td>\n<\/tr>\n
98<\/td>\n6.10 associate_supply_set <\/td>\n<\/tr>\n
100<\/td>\n6.11 begin_power_model (legacy) <\/td>\n<\/tr>\n
101<\/td>\n6.12 bind_checker <\/td>\n<\/tr>\n
103<\/td>\n6.13 connect_logic_net <\/td>\n<\/tr>\n
105<\/td>\n6.14 connect_supply_net <\/td>\n<\/tr>\n
107<\/td>\n6.15 connect_supply_set <\/td>\n<\/tr>\n
108<\/td>\n6.16 create_composite_domain <\/td>\n<\/tr>\n
110<\/td>\n6.17 create_hdl2upf_vct <\/td>\n<\/tr>\n
111<\/td>\n6.18 create_logic_net <\/td>\n<\/tr>\n
112<\/td>\n6.19 create_logic_port <\/td>\n<\/tr>\n
113<\/td>\n6.20 create_power_domain <\/td>\n<\/tr>\n
120<\/td>\n6.21 create_power_state_group <\/td>\n<\/tr>\n
122<\/td>\n6.22 create_power_switch <\/td>\n<\/tr>\n
129<\/td>\n6.23 create_pst (legacy) <\/td>\n<\/tr>\n
130<\/td>\n6.24 create_supply_net <\/td>\n<\/tr>\n
134<\/td>\n6.25 create_supply_port <\/td>\n<\/tr>\n
135<\/td>\n6.26 create_supply_set <\/td>\n<\/tr>\n
137<\/td>\n6.27 create_upf2hdl_vct <\/td>\n<\/tr>\n
138<\/td>\n6.28 define_power_model <\/td>\n<\/tr>\n
140<\/td>\n6.29 describe_state_transition (deprecated)
6.30 end_power_model (legacy) <\/td>\n<\/tr>\n
141<\/td>\n6.31 find_objects <\/td>\n<\/tr>\n
145<\/td>\n6.32 load_simstate_behavior <\/td>\n<\/tr>\n
146<\/td>\n6.33 load_upf <\/td>\n<\/tr>\n
147<\/td>\n6.34 load_upf_protected (deprecated)
6.35 map_power_switch <\/td>\n<\/tr>\n
148<\/td>\n6.36 map_repeater_cell <\/td>\n<\/tr>\n
149<\/td>\n6.37 map_retention_cell <\/td>\n<\/tr>\n
153<\/td>\n6.38 name_format <\/td>\n<\/tr>\n
154<\/td>\n6.39 save_upf <\/td>\n<\/tr>\n
155<\/td>\n6.40 set_correlated <\/td>\n<\/tr>\n
156<\/td>\n6.41 set_design_attributes <\/td>\n<\/tr>\n
157<\/td>\n6.42 set_design_top <\/td>\n<\/tr>\n
158<\/td>\n6.43 set_domain_supply_net (legacy) <\/td>\n<\/tr>\n
159<\/td>\n6.44 set_equivalent <\/td>\n<\/tr>\n
161<\/td>\n6.45 set_isolation <\/td>\n<\/tr>\n
168<\/td>\n6.46 set_level_shifter <\/td>\n<\/tr>\n
174<\/td>\n6.47 set_partial_on_translation <\/td>\n<\/tr>\n
176<\/td>\n6.48 set_port_attributes <\/td>\n<\/tr>\n
182<\/td>\n6.49 set_repeater <\/td>\n<\/tr>\n
186<\/td>\n6.50 set_retention <\/td>\n<\/tr>\n
190<\/td>\n6.51 set_retention_elements <\/td>\n<\/tr>\n
191<\/td>\n6.52 set_scope <\/td>\n<\/tr>\n
192<\/td>\n6.53 set_simstate_behavior <\/td>\n<\/tr>\n
195<\/td>\n6.54 set_variation <\/td>\n<\/tr>\n
196<\/td>\n6.55 sim_assertion_control <\/td>\n<\/tr>\n
198<\/td>\n6.56 sim_corruption_control <\/td>\n<\/tr>\n
201<\/td>\n6.57 sim_replay_control <\/td>\n<\/tr>\n
203<\/td>\n6.58 upf_version <\/td>\n<\/tr>\n
204<\/td>\n6.59 use_interface_cell <\/td>\n<\/tr>\n
206<\/td>\n7. Power-management cell definition commands
7.1 Introduction <\/td>\n<\/tr>\n
207<\/td>\n7.2 define_always_on_cell <\/td>\n<\/tr>\n
208<\/td>\n7.3 define_diode_clamp <\/td>\n<\/tr>\n
209<\/td>\n7.4 define_isolation_cell <\/td>\n<\/tr>\n
212<\/td>\n7.5 define_level_shifter_cell <\/td>\n<\/tr>\n
217<\/td>\n7.6 define_power_switch_cell <\/td>\n<\/tr>\n
219<\/td>\n7.7 define_retention_cell <\/td>\n<\/tr>\n
221<\/td>\n8. UPF processing
8.1 Overview <\/td>\n<\/tr>\n
222<\/td>\n8.2 Data requirements
8.3 Processing phases <\/td>\n<\/tr>\n
226<\/td>\n8.4 Error checking
9. Simulation semantics
9.1 Supply network creation <\/td>\n<\/tr>\n
228<\/td>\n9.2 Supply network simulation <\/td>\n<\/tr>\n
229<\/td>\n9.3 Power state simulation <\/td>\n<\/tr>\n
232<\/td>\n9.4 Power state transition detection <\/td>\n<\/tr>\n
233<\/td>\n9.5 Simstate simulation <\/td>\n<\/tr>\n
235<\/td>\n9.6 Transitioning from one simstate state to another <\/td>\n<\/tr>\n
236<\/td>\n9.7 Simulation of retention <\/td>\n<\/tr>\n
242<\/td>\n9.8 Simulation of isolation <\/td>\n<\/tr>\n
243<\/td>\n9.9 Simulation of level-shifting
9.10 Simulation of repeaters
10. UPF information model
10.1 Overview <\/td>\n<\/tr>\n
244<\/td>\n10.2 Components of UPF information model <\/td>\n<\/tr>\n
245<\/td>\n10.3 Identifiers in information model (IDs) <\/td>\n<\/tr>\n
248<\/td>\n10.4 Classification of objects <\/td>\n<\/tr>\n
254<\/td>\n10.5 Example of design hierarchy <\/td>\n<\/tr>\n
255<\/td>\n10.6 Object definitions <\/td>\n<\/tr>\n
314<\/td>\n11. Information model application programmable interface (API)
11.1 Tcl interface <\/td>\n<\/tr>\n
324<\/td>\n11.2 HDL interface <\/td>\n<\/tr>\n
388<\/td>\nAnnex A (informative) Bibliography <\/td>\n<\/tr>\n
389<\/td>\nAnnex B (normative) Value conversion tables
B.1 Overview
B.2 VHDL_SL2UPF
B.3 UPF2VHDL_SL
B.4 VHDL_SL2UPF_GNDZERO <\/td>\n<\/tr>\n
390<\/td>\nB.5 UPF_GNDZERO2VHDL_SL
B.6 SV_LOGIC2UPF
B.7 UPF2SV_LOGIC
B.8 SV_LOGIC2UPF_GNDZERO
B.9 UPF_GNDZERO2SV_LOGIC <\/td>\n<\/tr>\n
391<\/td>\nB.10 VHDL_TIED_HI
B.11 SV_TIED_HI
B.12 VHDL_TIED_LO
B.13 SV_TIED_LO <\/td>\n<\/tr>\n
392<\/td>\nAnnex C (informative) UPF query examples
C.1 Overview
C.2 Utility procs <\/td>\n<\/tr>\n
393<\/td>\nC.3 High-level procs <\/td>\n<\/tr>\n
395<\/td>\nC.4 Superseded UPF queries <\/td>\n<\/tr>\n
397<\/td>\nAnnex D (informative) Replacing deprecated and legacy commands and options
D.1 Overview
D.2 Deprecated and legacy constructs <\/td>\n<\/tr>\n
399<\/td>\nD.3 Recommendations for replacing deprecated and legacy constructs <\/td>\n<\/tr>\n
402<\/td>\nAnnex E (informative) Low-power design methodology
E.1 Overview
E.2 Simple System on Chip (SoC) example design <\/td>\n<\/tr>\n
405<\/td>\nE.3 Design, verification, and implementation flow <\/td>\n<\/tr>\n
408<\/td>\nE.4 Power intent of the example design <\/td>\n<\/tr>\n
429<\/td>\nAnnex F (informative) Power-management cell definitions in UPF and Liberty
F.1 Introduction
F.2 define_always_on_cell <\/td>\n<\/tr>\n
431<\/td>\nF.3 define_diode_clamp <\/td>\n<\/tr>\n
432<\/td>\nF.4 define_isolation_cell <\/td>\n<\/tr>\n
435<\/td>\nF.5 define_level_shifter_cell <\/td>\n<\/tr>\n
437<\/td>\nF.6 define_power_switch_cell <\/td>\n<\/tr>\n
439<\/td>\nF.7 define_retention_cell <\/td>\n<\/tr>\n
443<\/td>\nAnnex G (informative) Power-management cell modeling examples
G.1 Overview
G.2 Modeling always-on cells <\/td>\n<\/tr>\n
449<\/td>\nG.3 Modeling cells with internal diodes <\/td>\n<\/tr>\n
451<\/td>\nG.4 Modeling isolation cells <\/td>\n<\/tr>\n
468<\/td>\nG.5 Modeling level-shifters <\/td>\n<\/tr>\n
485<\/td>\nG.6 Modeling power-switch cells <\/td>\n<\/tr>\n
495<\/td>\nG.7 Modeling state retention cells <\/td>\n<\/tr>\n
507<\/td>\nAnnex H (informative) IP power modeling for system-level design
H.1 Introduction
H.2 Overview of system-level IP power models <\/td>\n<\/tr>\n
508<\/td>\nH.3 Content of system-level IP power models <\/td>\n<\/tr>\n
509<\/td>\nH.4 Power calculation using power functions <\/td>\n<\/tr>\n
511<\/td>\nH.5 Power model structure <\/td>\n<\/tr>\n
512<\/td>\nH.6 Power model instantiation\u2014example approach <\/td>\n<\/tr>\n
514<\/td>\nAnnex I (normative) Switching Activity Interchange Format <\/td>\n<\/tr>\n
515<\/td>\nI.1 Syntactic conventions <\/td>\n<\/tr>\n
516<\/td>\nI.2 Lexical conventions <\/td>\n<\/tr>\n
519<\/td>\nI.3 Backward SAIF file <\/td>\n<\/tr>\n
535<\/td>\nI.4 Library forward SAIF file <\/td>\n<\/tr>\n
543<\/td>\nI.5 RTL forward SAIF file <\/td>\n<\/tr>\n
548<\/td>\nBack cover <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":"

IEEE Standard for Design and Verification of Low-Power, Energy-Aware Electronic Systems<\/b><\/p>\n\n\n\n\n
Published By<\/td>\nPublication Date<\/td>\nNumber of Pages<\/td>\n<\/tr>\n
IEEE<\/b><\/a><\/td>\n2019<\/td>\n548<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n","protected":false},"featured_media":211714,"template":"","meta":{"rank_math_lock_modified_date":false,"ep_exclude_from_search":false},"product_cat":[2644],"product_tag":[],"class_list":{"0":"post-211709","1":"product","2":"type-product","3":"status-publish","4":"has-post-thumbnail","6":"product_cat-ieee","8":"first","9":"instock","10":"sold-individually","11":"shipping-taxable","12":"purchasable","13":"product-type-simple"},"_links":{"self":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product\/211709","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product"}],"about":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/types\/product"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media\/211714"}],"wp:attachment":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media?parent=211709"}],"wp:term":[{"taxonomy":"product_cat","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_cat?post=211709"},{"taxonomy":"product_tag","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_tag?post=211709"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}